Datasheet LTC4305 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | 2-Channel, 2-Wire Bus Multiplexer with Capacitance Buffering |
| Páginas / Página | 20 / 9 — OPERATIO. Register 2 (02h). Register 3 (03h). BIT NAME. TYPE* … |
| Formato / tamaño de archivo | PDF / 256 Kb |
| Idioma del documento | Inglés |
OPERATIO. Register 2 (02h). Register 3 (03h). BIT NAME. TYPE* DESCRIPTION. TIMSET1. TIMSET0. TIMEOUT MODE
Línea de modelo para esta hoja de datos
Versión de texto del documento
LTC4305
U OPERATIO Register 2 (02h) Register 3 (03h) BIT NAME TYPE* DESCRIPTION BIT NAME TYPE* DESCRIPTION
d7 Reserved R Not Used d7 Bus 1 FET State R/W Sets and indicates state of FET d6 Reserved R Not Used switches connected to downstream bus 1 d5 Connection R/W Sets logic requirements for 0 = switch open (default) Requirement downstream buses to be connected 1 = switch closed to upstream bus 0 = Bus Logic State bits (see register d6 Bus 2 FET State R/W Sets and indicates state of FET 3) of buses to be connected must be switches connected to downstream high for connection to occur (default) bus 2 1 = Connect regardless of 0 = switch open (default) downstream logic state 1 = switch closed d4 Reserved R Not Used d5 Reserved R Not Used d3 Reserved R Not Used d4 Reserved R Not Used d2 Mass Write Enable R/W Enable Mass Write Address using d3 Bus 1 Logic State R Indicates logic state of downstream address (1011 110)b bus 1; only valid when disconnected 0 = Disable Mass Write from upstream bus† 1 = Enable Mass Write (default) 0 = SDA1, SCL1 or both are below 1V 1 = SDA1 and SCL1 are both above d1 Timeout Mode Bit 1 R/W Stuck Low Timeout Set Bit 1** 1V d0 Timeout Mode Bit 0 R/W Stuck Low Timeout Set Bit 0** d2 Bus 2 Logic State R Indicates logic state of downstream * For Type, “R/W” = Read Write, “R” = Read Only bus 2; only valid when disconnected ** from upstream bus†
TIMSET1 TIMSET0 TIMEOUT MODE
0 = SDA2, SCL2 or both are below 1V 1 = SDA2 and SCL2 are both above 0 0 Timeout Disabled (Default) 1V 0 1 Timeout After 30ms d1 Reserved R Not Used 1 0 Timeout After 15ms d0 Reserved R Not Used 1 1 Timeout After 7.5ms * For Type, “R/W” = Read Write, “R” = Read Only † These bits are meant to give the logic state of disconnected downstream buses to the master, so that the master can choose not to connect to a low downstream bus. A given bit is a “don’t care” if its associated downstream bus is already connected to the upstream bus. 4305f 9
U OPERATIO Register 2 (02h) Register 3 (03h) BIT NAME TYPE* DESCRIPTION BIT NAME TYPE* DESCRIPTION
d7 Reserved R Not Used d7 Bus 1 FET State R/W Sets and indicates state of FET d6 Reserved R Not Used switches connected to downstream bus 1 d5 Connection R/W Sets logic requirements for 0 = switch open (default) Requirement downstream buses to be connected 1 = switch closed to upstream bus 0 = Bus Logic State bits (see register d6 Bus 2 FET State R/W Sets and indicates state of FET 3) of buses to be connected must be switches connected to downstream high for connection to occur (default) bus 2 1 = Connect regardless of 0 = switch open (default) downstream logic state 1 = switch closed d4 Reserved R Not Used d5 Reserved R Not Used d3 Reserved R Not Used d4 Reserved R Not Used d2 Mass Write Enable R/W Enable Mass Write Address using d3 Bus 1 Logic State R Indicates logic state of downstream address (1011 110)b bus 1; only valid when disconnected 0 = Disable Mass Write from upstream bus† 1 = Enable Mass Write (default) 0 = SDA1, SCL1 or both are below 1V 1 = SDA1 and SCL1 are both above d1 Timeout Mode Bit 1 R/W Stuck Low Timeout Set Bit 1** 1V d0 Timeout Mode Bit 0 R/W Stuck Low Timeout Set Bit 0** d2 Bus 2 Logic State R Indicates logic state of downstream * For Type, “R/W” = Read Write, “R” = Read Only bus 2; only valid when disconnected ** from upstream bus†
TIMSET1 TIMSET0 TIMEOUT MODE
0 = SDA2, SCL2 or both are below 1V 1 = SDA2 and SCL2 are both above 0 0 Timeout Disabled (Default) 1V 0 1 Timeout After 30ms d1 Reserved R Not Used 1 0 Timeout After 15ms d0 Reserved R Not Used 1 1 Timeout After 7.5ms * For Type, “R/W” = Read Write, “R” = Read Only † These bits are meant to give the logic state of disconnected downstream buses to the master, so that the master can choose not to connect to a low downstream bus. A given bit is a “don’t care” if its associated downstream bus is already connected to the upstream bus. 4305f 9