Datasheet LTC4302-1, LTC4302-2 (Analog Devices) - 9

LTC4302-1/LTC4302-2
U OPERATIO
broken up into 9-bit segments, one byte followed by one byte of information was received. The acknowledge re- bit for acknowledging. For example, sending out an ad- lated clock pulse is generated by the master. The transmit- dress consists of 7-bits of device address, 1-bit that ter master releases the SDA line (HIGH) during the ac- signals whether a read or write operation will be per- knowledge clock pulse. The slave-receiver must pull down formed and then 1 more bit to allow the slave to acknowl- the SDA line during the acknowledge clock pulse so that it edge. There is no theoretical limit to how many total bytes remains stable LOW during the HIGH period of this clock can be exchanged in a given transmission. pulse. I2C and SMBus are very similar specifications, SMBus When a slave-receiver doesn’t acknowledge the slave having been derived from I2C. In general, SMBus is address (for example, it’s unable to receive because it’s targeted to low power devices (particularly battery pow- performing a real-time function), the data line must be left ered ones) and emphasizes low power consumption while HIGH by the slave. The master can then generate a STOP I2C is targeted to higher speed systems where the power condition to abort the transfer. consumption of the bus is not as critical. I2C has three If a slave receiver does acknowledge the slave address but different specifications for three different maximum speeds, some time later in the transfer cannot receive any more these being standard mode (100kHz max), fast mode data bytes, the master must again abort the transfer. This (400kHz max), and Hs mode (3.4MHz max). Standard and is indicated by the slave not generating the acknowledge fast mode are not radically different, but Hs mode is very on the first byte to follow. The slave leaves the data line different from a hardware and software perspective and HIGH and the master generates the STOP condition. When requires an initiating command at standard or fast speed the master is reading data from the slave, the master before data can start transferring at Hs speed. SMBus acknowledges each byte read except for the last byte read. simply specifies a 100kHz maximum speed. The master signals a not acknowledge when no other data is to be read and carries out the STOP condition.
The START and STOP Conditions
When the bus is not in use, both SCL and SDA must be
Address Byte and Setting the LTC4302’s Address
high. A bus master signals the beginning of a transmission The LTC4302’s address is set by connecting ADDRESS to with a START condition by transitioning SDA from high to a resistive divider between V low while SCL is high. When the master has finished CC and ground. The voltage on ADDRESS is converted into a 5-bit digital word by an A/D communicating with the slave, it issues a STOP condition converter, as shown in Figure 1. This 5-bit word sets the by transitioning SDA from low to high while SCL is high. 5 LSB’s of the LTC4302’s address; its two MSB’s are The bus is then free for another transmission. always “11”. Using 1% resistors, the voltage at ADDRESS is set 0.5LSB away from each code transition. For ex-
Acknowledge
ample, with VCC=5V, 1LSB=5V/32 codes = 156.25mV/ The acknowledge signal is used for handshaking between code. To set an address of 00, set ADDRESS to 0V + the master and the slave. An acknowledge (LOW active) 0.5LSB = 78.125mV. generated by the slave lets the master know that the latest VCC R1 ADDRESS 5 WIRE 5-BIT 4 A/D R2 4302 F01
Figure 1. Address Compare Circuitry
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