Datasheet AD8307 (Analog Devices) - 9

AD8307 Data Sheet 2V VOUT CH1 500mV V CH1 OUT CH1 200mV CH 1 CH1 GND VENB CH 2 INPUT SIGNAL CH2 CH2 GND GND
18 15 0 0
CH2 2.00V 500ns
2-
CH2 1.00V 200ns
82- 08 010 01 Figure 15. Power-Up Response Time Figure 18. VOUT Rise Time
CH1 500mV V CH1 200mV OUT 2.5V CH 1 INPUT SIGNAL CH2 V CH2 ENB GND CH 2 VOUT CH1 CH1 GND GND
6 -019 1
CH2 1.00V 200ns
-0 82
CH2 2.00V 500ns
82 10 0 10 0 Figure 19. Large Signal Response Time Figure 16. Power-Down Response Time
HP8648B 10MHz REF CLK EXT TRIG TRIG SIGNAL HP8112A OUT VPS = 5.0V GENERATOR PULSE MODE IN OUT PULSE PULSE GENERATOR HP8648B SYNCH OUT VPS = 5.0V 0.1µF HP8112A MODULATION SIGNAL PULSE MODE GENERATOR GENERATOR 0.1µF 1nF 1nF OUT RF OUT RF OUT NC NC 8 7 6 5 8 7 6 5 INP VPS ENB INT INP VPS ENB INT 52.3Ω 52.3Ω AD8307 AD8307 INM COM OFS OUT INM COM OFS OUT 1 2 3 4 1 2 3 4 NC TEK744A NC TEK744A SCOPE SCOPE 1nF TEK P6204 TRIG 1nF TEK P6139A TRIG FET PROBE 10x PROBE
7 020 01
NC = NO CONNECT
2- 082- 08
NC = NO CONNECT
01 01 Figure 17. Test Setup for Power-Up/Power-Down Response Time Figure 20. Test Setup for VOUT Pulse Response Rev. E | Page 8 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS LOG AMP THEORY PROGRESSIVE COMPRESSION DEMODULATING LOG AMPS INTERCEPT CALIBRATION OFFSET CONTROL EXTENSION OF RANGE INTERFACES ENABLE INTERFACE INPUT INTERFACE OFFSET INTERFACE OUTPUT INTERFACE THEORY OF OPERATION BASIC CONNECTIONS INPUT MATCHING NARROW-BAND MATCHING SLOPE AND INTERCEPT ADJUSTMENTS APPLICATIONS INFORMATION BUFFERED OUTPUT FOUR-POLE FILTER 1 µW TO 1 kW 50 Ω POWER METER MEASUREMENT SYSTEM WITH 120 dB DYNAMIC RANGE OPERATION AT LOW FREQUENCIES OUTLINE DIMENSIONS ORDERING GUIDE