Datasheet AD8307 (Analog Devices)

Low Cost, DC to 500 MHz, 92 dB Logarithmic Amplifier Data Sheet AD8307 FEATURES FUNCTIONAL BLOCK DIAGRAM Complete multistage logarithmic amplifier AD8307 92 dB dynamic range: −75 dBm to +17 dBm to −90 dBm BAND GAP REFERENCE VPS 7 7.5mA 6 ENB using matching network AND BIASING Single supply of 2.7 V minimum at 7.5 mA typical SIX 14.3dB 900MHz AMPLIFIER STAGES 5 INT DC to 500 MHz operation, ±1 dB linearity +INP INP 8 Slope of 25 mV/dB, intercept of −84 dBm 1.1kΩ MIRROR INM 1 –INP 2µA Highly stable scaling over temperature 3 /dB 4 OUT 2 Fully differential dc-coupled signal path NINE DETECTOR CELLS 12.5kΩ SPACED 14.3dB 100 ns power-up time, 150 μA sleep current COM 2 COM APPLICATIONS INPUT-OFFSET 3 OFS COMPENSATION LOOP
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Conversion of signal level to decibel form
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Transmitter antenna power measurement
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Receiver signal strength indication (RSSI) Low cost radar and sonar signal processing Network and spectrum analyzers (to 120 dB) Signal level determination down to 20 Hz True decibel ac mode for multimeters GENERAL DESCRIPTION
The AD8307 is the first logarithmic amplifier made available in
Table 1. Next Generation Upgrades for the AD8307
an 8-lead SOIC_N package. It is a complete 500 MHz monolithic
Device No. Product Description
demodulating logarithmic amplifier based on the progressive AD8310 15 ns Response Time, Buffered Output compression (successive detection) technique, providing a ADL5513 Lower Input Range (80 dB), Operation to 4 GHz, dynamic range of 92 dB to ±3 dB law conformance and 88 dB to Higher Power Consumption a tight ±1 dB error bound at all frequencies up to 100 MHz. The AD8309 Higher Input Range (100 dB), Limiter Output AD8307 is extremely stable and easy to use, requiring no significant external components. A single-supply voltage of 2.7 V to 5.5 V at 7.5 mA is needed. A fast acting CMOS-compatible control pin can disable the AD8307 to a standby current of 150 μA. The AD8307 operates over the industrial temperature range of −40°C to +85°C and is available in an 8-lead SOIC package and an 8-lead PDIP.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS LOG AMP THEORY PROGRESSIVE COMPRESSION DEMODULATING LOG AMPS INTERCEPT CALIBRATION OFFSET CONTROL EXTENSION OF RANGE INTERFACES ENABLE INTERFACE INPUT INTERFACE OFFSET INTERFACE OUTPUT INTERFACE THEORY OF OPERATION BASIC CONNECTIONS INPUT MATCHING NARROW-BAND MATCHING SLOPE AND INTERCEPT ADJUSTMENTS APPLICATIONS INFORMATION BUFFERED OUTPUT FOUR-POLE FILTER 1 µW TO 1 kW 50 Ω POWER METER MEASUREMENT SYSTEM WITH 120 dB DYNAMIC RANGE OPERATION AT LOW FREQUENCIES OUTLINE DIMENSIONS ORDERING GUIDE