Datasheet AD8307 (Analog Devices) - 6

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Data Sheet AD8307 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INM 1 8 INP COM 2 7 VPS AD8307 OFS 3 TOP VIEW 6 ENB OUT (Not to Scale) 4 5 INT
02 0 2- 08 01 Figure 2. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 INM Signal Input Minus Polarity. Normally at VPOS/2. 2 COM Common Pin (Usually Grounded). 3 OFS Offset Adjustment. External capacitor connection. 4 OUT Logarithmic (RSSI) Output Voltage. ROUT = 12.5 kΩ. 5 INT Intercept Adjustment, ±3 dB. (See the Slope and Intercept Adjustments section.) 6 ENB CMOS-Compatible Chip Enable. Active when high. 7 VPS Positive Supply: 2.7 V to 5.5 V. 8 INP Signal Input Plus Polarity. Normally at VPOS/2. Due to the symmetrical nature of the response, there is no special significance to the sign of the two input pins. DC resistance from INP to INM = 1.1 kΩ. Rev. E | Page 5 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS LOG AMP THEORY PROGRESSIVE COMPRESSION DEMODULATING LOG AMPS INTERCEPT CALIBRATION OFFSET CONTROL EXTENSION OF RANGE INTERFACES ENABLE INTERFACE INPUT INTERFACE OFFSET INTERFACE OUTPUT INTERFACE THEORY OF OPERATION BASIC CONNECTIONS INPUT MATCHING NARROW-BAND MATCHING SLOPE AND INTERCEPT ADJUSTMENTS APPLICATIONS INFORMATION BUFFERED OUTPUT FOUR-POLE FILTER 1 µW TO 1 kW 50 Ω POWER METER MEASUREMENT SYSTEM WITH 120 dB DYNAMIC RANGE OPERATION AT LOW FREQUENCIES OUTLINE DIMENSIONS ORDERING GUIDE