Datasheet ADL5205 (Analog Devices) - 6

Data Sheet ADL5205 TIMING SPECIFICATIONS Table 2. SPI Timing Parameters Parameter Symbol Min Typ Max Unit Test Conditions/Comments
CSA or CSB to SCLK Setup Time t 20 ns CS SDIO to SCLK Setup Time tDS 10 ns SCLK to SDIO Hold Time tDH 10 ns SCLK Pulse Width tPW 25 ns SCLK Cycle Time tSCLK 50 ns SCLK to CSA or CSB Setup Time tCH 10 ns SCLK to SDIO Output Valid Delay tDV 20 ns During readback
Timing Diagrams tSCLK tPW SCLK tCH tCS tDV ___ ___ CSA, CSB tDS tDH
02
SDIO DNC DNC DNC DNC DNC DNC DNC R/W FA1 FA0 D5 D4 D3 D2 D1 D0
0 88- 134 Figure 2. SPI Interface Read/Write Mode Timing Diagram
tDS tDS UPDN_DAT_x tPW UPDN_CLK_x UP DOWN RESET
003
tDS t t DH DH
88- 134 Figure 3. Up/Down Gain Control Timing Diagram
LATCHA, LATCHB A5 TO A0 B5 TO B0
004
t
88-
DH
134 Figure 4. Parallel Mode Timing Diagram Rev. 0 | Page 5 of 31 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE JUNCTION TO BOARD THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BASIC STRUCTURE CONTROL/LOGIC CIRCUITRY COMMON-MODE VOLTAGE APPLICATIONS INFORMATION BASIC CONNECTIONS DIGITAL INTERFACE OVERVIEW Parallel Digital Interface Serial Peripheral Interface (SPI) Up/Down Interface SPI READ ADC INTERFACING NOISE FIGURE vs. GAIN SETTING EVALUATION BOARD OVERVIEW POWER SUPPLY INTERFACE SIGNAL INPUTS AND OUTPUTS MANUAL CONTROLS Mode Switches Channel Control Switches PARALLEL INTERFACE SERIAL INTERFACE STANDARD DEVELOPMENT PLATFORM (SDP) INTERFACE EVALUATION BOARD CONTROL SOFTWARE COMMAND LINE CONTROL PROGRAM GRAPHICAL USER INTERFACE (GUI) PROGRAM EVALUATION BOARD SCHEMATICS AND LAYOUT BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE