Datasheet ADL5205 (Analog Devices)
Fabricante | Analog Devices |
Descripción | Dual, 35 dB Range, 1 dB Step Size DGA |
Páginas / Página | 32 / 1 — Dual, 35 dB Range, 1 dB Step Size DGA. Data Sheet. ADL5205. FEATURES. … |
Formato / tamaño de archivo | PDF / 1.7 Mb |
Idioma del documento | Inglés |
Dual, 35 dB Range, 1 dB Step Size DGA. Data Sheet. ADL5205. FEATURES. FUNCTIONAL BLOCK DIAGRAM
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Dual, 35 dB Range, 1 dB Step Size DGA Data Sheet ADL5205 FEATURES FUNCTIONAL BLOCK DIAGRAM Dual, independent, digitally controlled gain amplifier (DGA) SIDE A SPI WITH FA, −9 dB to +26 dB gain range PARALLEL WITH LATCH, UP/DOWN PWUPA VPOS 1 dB step size, ±0.2 dB accuracy at 200 MHz 100 Ω differential input resistance 10 Ω differential output resistance LOGIC 1.2 dB change in noise figure for first 12 dB of gain reduction Output third-order intercept (OIP3): 48.5 dBm at 200 MHz, 5 V, VINA+ 14dB 0dB TO 23dB VOUTA– 100 TO Ω 10Ω high performance mode 26dB VINA– VOUTA+ −3 dB bandwidth: 1700 MHz typical in high performance mode MODE0 CONTROL Multiple control interface options MODE1 CIRCUITRY Parallel 6-bit control interface with latch PM Serial peripheral interface (SPI) with fast attack Gain step up/down interface VINB+ 14dB VOUTB– 0dB TO 23dB TO Wide input dynamic range 100Ω 10Ω VINB– 26dB VOUTB+ Low power mode Power-down control LOGIC Single 3.3 V or 5 V supply operation ADL5205 40-lead, 6 mm × 6 mm LFCSP package SIDE B PWUPB GND APPLICATIONS SPI WITH FA,
001
PARALLEL WITH LATCH, UP/DOWN
13488-
Differential analog-to-digital converter (ADC) drivers
Figure 1.
High intermediate frequency (IF) sampling receivers High output power IF amplification Instrumentation GENERAL DESCRIPTION
The ADL5205 is a digitally controlled, wide bandwidth, variable low power mode. When disabled, the ADL5205 consumes only gain dual amplifier (DGA) that provides precise gain control, high 14 mA and offers excel ent input to output isolation. The gain output third-order intercept (OIP3) and a near constant noise setting is preserved when the device is disabled. figure for the first 12 dB of attenuation. The excel ent OIP3 Fabricated on the Analog Devices, Inc., high speed, silicon performance of 48.5 dBm (at 200 MHz, 5 V, high performance germanium (SiGe) complementary BiCMOS process, the mode, and maximum gain) makes the ADL5205 an excellent ADL5205 provides precise gain adjustment capabilities with good gain control device for a variety of receiver applications. distortion performance. The ADL5205 amplifier comes in a For wide input dynamic range applications, the ADL5205 compact, thermal y enhanced, 6 mm × 6 mm, 40-lead LFCSP provides a broad 35 dB gain range with a 1 dB step size. The package and operates over the temperature range of −40°C to gain is adjustable through multiple gain control and interface +85°C. options: parallel, SPI, or gain step up/down control. Note that throughout this data sheet, multifunction pins, such The two channels of the ADL5205 can be powered up as CSA/A3, are referred to by the entire pin name or by a single independently by applying the appropriate logic level to the function of the pin, for example, CSA, when only that function PWUPA and PWUPB pins. The quiescent current of the ADL5205 is relevant. is typically 175 mA for high performance mode and 135 mA for
Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE JUNCTION TO BOARD THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BASIC STRUCTURE CONTROL/LOGIC CIRCUITRY COMMON-MODE VOLTAGE APPLICATIONS INFORMATION BASIC CONNECTIONS DIGITAL INTERFACE OVERVIEW Parallel Digital Interface Serial Peripheral Interface (SPI) Up/Down Interface SPI READ ADC INTERFACING NOISE FIGURE vs. GAIN SETTING EVALUATION BOARD OVERVIEW POWER SUPPLY INTERFACE SIGNAL INPUTS AND OUTPUTS MANUAL CONTROLS Mode Switches Channel Control Switches PARALLEL INTERFACE SERIAL INTERFACE STANDARD DEVELOPMENT PLATFORM (SDP) INTERFACE EVALUATION BOARD CONTROL SOFTWARE COMMAND LINE CONTROL PROGRAM GRAPHICAL USER INTERFACE (GUI) PROGRAM EVALUATION BOARD SCHEMATICS AND LAYOUT BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE