Datasheet AD5379 (Analog Devices) - 6

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AD5379 Parameter A Version1 Unit Test Conditions/Comments2
Power Supply Sensitivity2 ∆ Full Scale/∆ VDD −75 dB typ ∆ Full Scale/∆ VSS −75 dB typ ∆ Full Scale/∆ VCC −90 dB typ ICC 5 mA max VCC = 5.5 V, VIH = VCC, VIL = GND IDD 28 mA max Outputs unloaded (typically 20 mA) ISS 23 mA max Outputs unloaded (typically 15 mA) Power Dissipation Power Dissipation Unloaded (P) 850 mW max VDD = 16.5 V, VSS = −16.5 V Power Dissipation Loaded (PTOTAL) 2000 mW max PTOTAL = P + Σ(VDD − VO) × ISOURCE + Σ(VO − VSS) × ISINK Junction Temperature 130 °C max T 3 J = TA + PTOTAL × θJ 1 Temperature range for A Version: −40°C to +85°C. Typical specifications are at 25°C. 2 Guaranteed by design and characterization, not production tested. 3 Where θJ represents the package thermal impedance.
AC CHARACTERISTICS
VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; VREF(+) = 5 V; VREF(−) = −3.5 V; AGND = DGND = REFGND = 0 V; VBIAS = 5 V; CL = 220 pF; RL = 11 kΩ to 3 V; gain = 1; offset = 0 V.
Table 3. Parameter A Version 1 Unit Test Conditions/Comments
DYNAMIC PERFORMANCE Output Voltage Settling Time 20 μs typ Full-scale change to ±1/2 LSB 30 μs max DAC latch contents alternately loaded with all 0s and all 1s Slew Rate 1 V/μs typ Digital-to-Analog Glitch Energy 20 nV-s typ Glitch Impulse Peak Amplitude 15 mV max Channel-to-Channel Isolation 100 dB typ VREF(+) = 2 V p-p, (1 VBIAS) 1 kHz, VREF(−) = −1 V DAC-to-DAC Crosstalk 40 nV-s typ Between DACs inside a group (see the Terminology section) 10 nV-s typ Between DACs from different groups Digital Crosstalk 0.1 nV-s typ Digital Feedthrough 1 nV-s typ Effect of input bus activity on DAC output under test Output Noise Spectral Density @ 1 kHz 350 nV/(Hz)1/2 typ VREF(+) = VREF(−) = 0 V 1 Guaranteed by design and characterization, not production tested. Rev. B | Page 5 of 28 Document Outline FEATURES APPLICATIONS TABLE OF CONTENTS GENERAL DESCRIPTION SPECIFICATIONS AC CHARACTERISTICS TIMING CHARACTERISTICS SERIAL INTERFACE PARALLEL INTERFACE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS FUNCTIONAL DESCRIPTION DAC ARCHITECTURE—GENERAL CHANNEL GROUPS TRANSFER FUNCTION VBIAS FUNCTION REFERENCE SELECTION Reference Selection Example CALIBRATION Calibration Example CLEAR FUNCTION Hardware Clear Software Clear /BUSY AND /LDAC FUNCTIONS FIFO VS. NON-FIFO OPERATION /BUSY INPUT FUNCTION POWER-ON RESET FUNCTION /RESET INPUT FUNCTION INCREMENT/DECREMENT FUNCTION INTERFACES PARALLEL INTERFACE / CS Pin /WR Pin REG1, REG0 Pins DB13 to DB0 Pins A7 to A0 Pins SERIAL INTERFACE /SYNC , DIN, SCLK DCEN SDO Standalone Mode Daisy-Chain Mode DATA DECODING ADDRESS DECODING POWER SUPPLY DECOUPLING POWER-ON TYPICAL APPLICATION CIRCUIT OUTLINE DIMENSIONS ORDERING GUIDE