Datasheet AD7713 (Analog Devices) - 5

AD7713 Parameter A, S Versions1 Unit Conditions/Comments
AIN3 Positive Full-Scale Calibration Limit13 +(4.2 ⫻ VREF)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128). Offset Calibration Limit15 0 to VREF/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128). Input Span +(3.2 ⫻ VREF)/GAIN V min GAIN Is the Selected PGA Gain (Between 1 and 128). +(4.2 ⫻ VREF)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128). POWER REQUIREMENTS Power Supply Voltages AVDD Voltage16 5 to 10 V nom ±5% for Specified Performance. DVDD Voltage17 5 V nom ±5% for Specified Performance. Power Supply Currents AVDD Current 0.6 mA max AVDD = 5 V. 0.7 mA max AVDD = 10 V. DVDD Current 0.5 mA max fCLK IN = 1 MHz. Digital Inputs 0 V to DVDD. 1 mA max fCLK IN = 2 MHz. Digital Inputs 0 V to DVDD. Power Supply Rejection18 Rejection w.r.t. AGND. (AVDD and DVDD)19 dB typ Power Dissipation Normal Mode 5.5 mW max AVDD = DVDD = 5 V, fCLK IN = 1 MHz; Typically 3.5 mW. Standby (Power-Down) Mode 300 µW max AVDD = DVDD = 5 V, Typically 150 µW. NOTES 1 Temperature range is: A Version, –40°C to +85°C; S Version, –55°C to +125°C. 2 Applies after calibration at the temperature of interest. 3 Positive full-scale error applies to both unipolar and bipolar input ranges. 4 These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20 µV typical after self-calibration or background calibration. 5 Recalibration at any temperature or use of the background calibration mode will remove these drift errors. 6 These numbers are guaranteed by design and/or characterization. 7 The AIN1 and AIN2 analog inputs present a very high impedance dynamic load that varies with clock frequency and input sample rate. The maximum recom- mended source resistance depends on the selected gain. 8 The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2(–) inputs. The input voltage range on the AIN3 input is with respect to AGND. The absolute voltage on the AIN1 and AIN2 inputs should not go more positive than AV DD + 30 mV or more negative than AGND – 30 mV. 9 VREF = REF IN(+) – REF IN(–). 10 This common-mode voltage range is allowed, provided that the input voltage on AIN(+) and AIN(–) does not exceed AV DD + 30 mV and AGND – 30 mV. 11 This error can be removed using the system calibration capabilities of the AD7713. This error is not removed by the AD7713’s self-calibration feature. The offset drift on the AIN3 input is four times the value given in the Static Performance section of the specifications. 12 Guaranteed by design, not production tested. 13 After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, the device will output all 0s. 14These calibration and span limits apply provided the absolute voltage on the AIN1 and AIN2 analog inputs does not exceed AV DD + 30 mV or go more negative than AGND – 30 mV. 15 The offset calibration limit applies to both the unipolar zero point and the bipolar zero point. 16 Operating with AVDD voltages in the range 5.25 V to 10.5 V is guaranteed only over the 0°C to 70°C temperature range. 17 The ± 5% tolerance on the DVDD input is allowed provided that DVDD does not exceed AVDD by more than 0.3 V. 18 Measured at dc and applies in the selected pass band. PSRR at 50 Hz will exceed 120 dB with filter notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, or 50 Hz. PSRR at 60 Hz will exceed 120 dB with filter notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, or 60 Hz. 19 PSRR depends on gain: gain of 1 = 70 dB typ; gain of 2 = 75 dB typ; gain of 4 = 80 dB typ; gains of 8 to 128 = 85 dB typ. Specifications subject to change without notice. –4– REV. D Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTION TERMINOLOGY Integral Nonlinearity Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span CONTROL REGISTER (24 BITS) Filter Selection (FS11 to FS0) CIRCUIT DESCRIPTION THEORY OF OPERATION Input Sample Rate DIGITAL FILTERING Filter Characteristics Post Filtering Antialias Considerations ANALOG INPUT FUNCTIONS Analog Input Ranges Burn Out Current RTD Excitation Currents Bipolar/Unipolar Inputs REFERENCE INPUT USING THE AD7713 SYSTEM DESIGN CONSIDERATIONS Clocking System Synchronization Accuracy Autocalibration Self-Calibration System Calibration System Offset Calibration Background Calibration Span and Offset Limits POWER-UP AND CALIBRATION Drift Considerations POWER SUPPLIES AND GROUNDING DIGITAL INTERFACE Self-Clocking Mode Read Operation Write Operation External Clocking Mode Read Operation Write Operation SIMPLIFYING THE EXTERNAL CLOCKING MODE INTERFACE MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7713 to 8XC51 Interface AD7713 to 68HC11 Interface APPLICATIONS 4-Wire RTD Configurations 3-Wire RTD Configurations 4–20 mA Loop OTHER 24-BIT SIGNAL CONDITIONING ADCS AVAILABLE FROM ANALOG DEVICES AD7710 AD7711 AD7712 OUTLINE DIMENSIONS Revision History