Datasheet AD7713 (Analog Devices) - 4

AD7713 Parameter A, S Versions1 Unit Conditions/Comments
REFERENCE INPUT REF IN(+) – REF IN(–) Voltage 2.5 to AVDD/1.8 V min to V max For Specified Performance. Part Is Functional with Lower VREF Voltages. Input Sampling Rate, fS fCLK IN/512 Normal-Mode 50 Hz Rejection6 100 dB min For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz, ± 0.02 ⫻ fNOTCH. Normal-Mode 60 Hz Rejection6 100 dB min For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz, ± 0.02 ⫻ fNOTCH. Common-Mode Rejection (CMR) 100 dB min At DC. Common-Mode 50 Hz Rejection6 150 dB min For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz, ± 0.02 ⫻ fNOTCH. Common-Mode 60 Hz Rejection6 150 dB min For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz, ± 0.02 ⫻ fNOTCH. Common-Mode Voltage Range10 AGND to AVDD V min to V max DC Input Leakage Current @ 25°C 10 pA max TMIN to TMAX 1 nA max LOGIC INPUTS Input Current ±10 µA max All Inputs Except MCLK IN VINL, Input Low Voltage 0.8 V max VINH, Input High Voltage 2.0 V min MCLK IN Only VINL, Input Low Voltage 0.8 V max VINH, Input High Voltage 3.5 V min LOGIC OUTPUTS VOL, Output Low Voltage 0.4 V max ISINK = 1.6 mA. VOH, Output High Voltage 4.0 V min ISOURCE = 100 µA. Floating State Leakage Current ±10 µA max Floating State Output Capacitance12 9 pF typ TRANSDUCER BURN-OUT Current 1.2 µA nom Initial Tolerance @ 25°C ±10 % typ Drift 0.1 %/°C typ RTD EXCITATION CURRENTS (RTD1, RTD2) Output Current 200 µA nom Initial Tolerance @ 25°C ±20 % max Drift 20 ppm/°C typ Initial Matching @ 25°C ±1 % max Matching Between RTD1 and RTD2 Currents. Drift Matching 3 ppm/°C typ Matching Between RTD1 and RTD2 Current Drift. Line Regulation (AVDD) 200 nA/V max AVDD = 5 V. Load Regulation 200 nA/V max SYSTEM CALIBRATION AIN1, AIN2 Positive Full-Scale Calibration Limit13 +(1.05 ⫻ VREF)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128). Negative Full-Scale Calibration Limit13 –(1.05 ⫻ VREF)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128). Offset Calibration Limit14, 15 –(1.05 ⫻ VREF)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128). Input Span14 +(0.8 ⫻ VREF)/GAIN V min GAIN Is the Selected PGA Gain (Between 1 and 128). +(2.1 ⫻ VREF)/GAIN V max GAIN Is the Selected PGA Gain (Between 1 and 128). REV. D –3– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTION TERMINOLOGY Integral Nonlinearity Positive Full-Scale Error Unipolar Offset Error Bipolar Zero Error Bipolar Negative Full-Scale Error Positive Full-Scale Overrange Negative Full-Scale Overrange Offset Calibration Range Full-Scale Calibration Range Input Span CONTROL REGISTER (24 BITS) Filter Selection (FS11 to FS0) CIRCUIT DESCRIPTION THEORY OF OPERATION Input Sample Rate DIGITAL FILTERING Filter Characteristics Post Filtering Antialias Considerations ANALOG INPUT FUNCTIONS Analog Input Ranges Burn Out Current RTD Excitation Currents Bipolar/Unipolar Inputs REFERENCE INPUT USING THE AD7713 SYSTEM DESIGN CONSIDERATIONS Clocking System Synchronization Accuracy Autocalibration Self-Calibration System Calibration System Offset Calibration Background Calibration Span and Offset Limits POWER-UP AND CALIBRATION Drift Considerations POWER SUPPLIES AND GROUNDING DIGITAL INTERFACE Self-Clocking Mode Read Operation Write Operation External Clocking Mode Read Operation Write Operation SIMPLIFYING THE EXTERNAL CLOCKING MODE INTERFACE MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7713 to 8XC51 Interface AD7713 to 68HC11 Interface APPLICATIONS 4-Wire RTD Configurations 3-Wire RTD Configurations 4–20 mA Loop OTHER 24-BIT SIGNAL CONDITIONING ADCS AVAILABLE FROM ANALOG DEVICES AD7710 AD7711 AD7712 OUTLINE DIMENSIONS Revision History