Datasheet AD7891 (Analog Devices) - 8

AD7891 PARALLEL INTERFACE MODE FUNCTIONS PLCC Pin No. MQFP Pin No. Mnemonic Description
8, 31 2, 25 NC No Connect. The two NC pins on the device can be left unconnected. If they are to be connected to a voltage, it should be to ground potential. To ensure correct operation of the AD7891, neither of the NC pins should be connected to a logic high potential. 29 23 CS Chip Select Input. Active low logic input that is used in conjunction with to enable the data outputs and with WR to allow input data to be written to the part. 28 22 RD Read Input. Active low logic input that is used in conjunction with CS low to enable the data outputs. 27 21 WR Write Input. Active low logic input used in conjunction with CS to latch the mul- tiplexer address and software control information. The rising edge of this input also initiates an internal pulse. When using the software start facility, this pulse delays the point at which the track/hold goes into hold and conversion is initiated. This allows the multiplexer to settle and the acquisition time of the track/hold to elapse when a channel address is changed. If the SWCON bit of the control regis- ter is set to 1, when this pulse times out, the track/hold then goes into hold and conversion is initiated. If the SWCON bit of the control register is set to 0, the track/hold and conversion sequence are unaffected by WR operation.
Data I/O Lines
There are 12 data input/output lines on the AD7891. When the part is configured for parallel mode (MODE = 1), the output data from the part is provided at these 12 pins during a read operation. For a write operation in parallel mode, these lines provide access to the part’s control register.
Parallel Read Operation
During a parallel read operation, the 12 lines become the 12 data bits containing the conversion result from the AD7891. These data bits are labelled Data Bit 0 (LSB) to Data Bit 11 (MSB). They are three-state, TTL compatible outputs. Output data coding is twos complement when the data FORMAT bit of the control register is 1, and straight binary when the data FORMAT bit of the control register is 0.
PLCC Pin No. MQFP Pin No. Mnemonic Description
13 to 18, 7 to 12, DB0 to DB11 Data Bit 0 (LSB) to Data Bit 11 (MSB). Three-state TTL compatible 21 to 26 15 to 20 outputs that are controlled by the CS and RD inputs.
Parallel Write Operation
During a parallel write operation, the following functions can be written to the control register via the 12 data input/output pins.
PLCC Pin No. MQFP Pin No. Mnemonic Description
23 17 A0 Address Input. The status of this input during a parallel write operation is latched to the A0 bit of the control register (see Control Register section). 22 16 A1 Address Input. The status of this input during a parallel write operation is latched to the A1 bit of the control register (see Control Register section). 21 15 A2 Address Input. The status of this input during a parallel write operation is latched to the A2 bit of the control register (see Control Register section). 24 18 SWCON Software Conversion Start. The status of this input during a parallel write operation is latched to the SWCONV bit of the control register (see Control Register section). 25 19 SWSTBY Software Standby Control. The status of this input during a parallel write operation is latched to the SWSTBY bit of the control register (see Control Register section). 26 20 FORMAT Data Format Selection. The status of this input during a parallel write operation is latched to the FORMAT bit of the control register (see Control Register section). REV. D –7– Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS TIMING CHARACTERISTICS ORDERING GUIDE PIN CONFIGURATIONS PIN FUNCTION DESCRIPTIONS PARALLEL INTERFACE MODE FUNCTIONS Data I/O Lines Parallel Read Operation SERIAL INTERFACE MODE FUNCTIONS CONTROL REGISTER TERMINOLOGY Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Intermodulation Distortion Channel-to-Channel Isolation Relative Accuracy Differential Nonlinearity Positive Full-Scale Error (AD7891-1, ±10 V and ±5 V; AD7891-2, ±2.5 V) Positive Full-Scale Error (AD7891-2, 0 V to 5 V and 0 V to 2.5 V) Bipolar Zero Error (AD7891-1, ±10 V and ±5 V; AD7891-2, ±2.5 V) Unipolar Offset Error (AD7891-2, 0 V to 5 V and 0 V to 2.5 V) Negative Full-Scale Error (AD7891-1, ±10 V and ±5V; AD7891-2, ±2.5 V) Track/Hold Acquisition Time CONVERTER DETAILS INTERFACE INFORMATION Parallel Interface Mode Serial Interface Mode Simplifying the Serial Interface CIRCUIT DESCRIPTION Reference Analog Input Section Track/Hold Amplifier STANDBY Operation MICROPROCESSOR INTERFACING AD7891 to 8X51 Serial Interface AD7891 to 68HC11 Serial Interface AD7891 to ADSP-21xx Serial Interface AD7891 to DSP5600x Serial Interface AD7891 to TMS320xxx Serial Interface PARALLEL INTERFACING AD7891 to ADSP-21xx AD7891 to TMS32020, TMS320C25, and TMS320C5x AD7891 to TMS320C3x AD7891 to DSP5600x Power Supply Bypassing and Grounding AD7891 PERFORMANCE Linearity Noise Dynamic Performance Effective Number of Bits OUTLINE DIMENSIONS Revision History