Datasheet AD7859, AD7859L (Analog Devices) - 9

AD7859/AD7859L AD7859/AD7859L ON-CHIP REGISTERS
The AD7859/AD7859L powers up with a set of default conditions. The only writing that is required is to select the channel configu- ration. Without performing any other write operations, the AD7859/AD7859L still retains the flexibility for performing a full power- down and a full self-calibration. Extra features and flexibility such as performing different power-down options, different types of calibrations, including system cali- bration, and software conversion start can be selected by writing to the part. The AD7859/AD7859L contains a
Control register, ADC output data register, Status register, Test register
and
10 Cali- bration registers
. The control register is write-only, the ADC output data register and the status register are read-only, and the test and calibration registers are both read/write registers. The test register is used for testing the part and should not be written to.
Addressing the On-Chip Registers
Writing When writing to the AD7859/AD7859L, a 16-bit word of data must be transferred. The 16 bits of data is written as either a 16-bit word, or as two 8-bit bytes, depending on the logic level at the W/B pin. When W/B is high, the 16 bits are transferred on DB0 to DB15, where DB0 is the LSB and DB15 is the MSB of the write. When W/B is low, DB8/HBEN assumes its HBEN functionality and data is transferred in two 8-bit bytes on pins DB0 to DB7, pin DB0 being the LSB of each transfer and pin DB7 being the MSB. When writing to the AD7859/AD7859L in byte mode, the low byte must be written first followed by the high byte. The two MSBs of the complete 16-bit word, ADDR1 and ADDR0, are decoded to determine which register is addressed, and the 14 LSBs are writ- ten to the addressed register. Table I shows the decoding of the address bits, while Figure 2 shows the overall write register hierarchy.
Table I. Write Register Addressing ADDR1 ADDR0 Comment
0 0 This combination does not address any register. 0 1 This combination addresses the
TEST REGISTER
. The 14 LSBs of data are written to the test register. 1 0 This combination addresses the
CALIBRATION REGISTERS
. The 14 LSBs of data are written to the selected calibration register. 1 1 This combination addresses the
CONTROL REGISTER
. The 14 LSBs of data are written to the control register. Reading To read from the various registers the user must first write to Bits 6 and 7 in the Control Register, RDSLT0 and RDSLT1. These bits are decoded to determine which register is addressed during a read operation. Table II shows the decoding of the read address bits while Figure 3 shows the overall read register hierarchy. The power-up status of these bits is 00 so that the default read will be from the ADC output data register. As with writing to the AD7859/AD7859L either word or byte mode can be used. When reading from the calibration registers in byte mode, the low byte must be read first. Once the read selection bits are set in the control register all subsequent read operations that follow are from the selected register un- til the read selection bits are changed in the control register.
Table II. Read Register Addressing RDSLT1 RDSLT0 Comment
0 0 All successive read operations are from the
ADC OUTPUT DATA REGISTER
. This is the default power- up setting. There is always four leading zeros when reading from the ADC output data register. 0 1 All successive read operations are from the
TEST REGISTER
. 1 0 All successive read operations are from the
CALIBRATION REGISTERS
. 1 1 All successive read operations are from the
STATUS REGISTER
.
RDSLT1, RDSLT0 ADDR1, ADDR0 DECODE DECODE 00 01 10 11 01 10 11 ADC OUTPUT TEST CALIBRATION STATUS TEST CALIBRATION CONTROL DATA REGISTER REGISTER REGISTERS REGISTER REGISTER REGISTERS REGISTER GAIN (1) GAIN (1) GAIN (1) GAIN (1) OFFSET (1) OFFSET (1) OFFSET (1) GAIN (1) OFFSET (1) OFFSET (1) OFFSET (1) GAIN (1) DAC (8) DAC (8) 00 01 10 11 00 01 10 11 CALSLT1, CALSLT0 CALSLT1, CALSLT0 DECODE DECODE
Figure 2. Write Register Hierarchy/Address Decoding Figure 3. Read Register Hierarchy/Address Decoding –8– REV. A