Datasheet AD7859, AD7859L (Analog Devices) - 8

AD7859/AD7859L PIN FUNCTION DESCRIPTION Mnemonic Description
CONVST Convert Start. Logic input. A low to high transition on this input puts the track/hold into its hold mode and starts conversion. When this input is not used, it should be tied to DVDD. RD Read Input. Active low logic input. Used in conjunction with CS to read from internal registers. WR Write Input. Active low logic input. Used in conjunction with CS to write to internal registers. CS Chip Select Input. Active low logic input. The device is selected when this input is active. REFIN/ Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the REFOUT reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V and this appears at the pin. This pin can be overdriven by an external reference or can be taken as high as AVDD. When this pin is tied to AVDD, then the CREF1 pin should also be tied to AVDD. AVDD Analog Supply Voltage, +3.0 V to +5.5 V. AGND Analog Ground. Ground reference for track/hold, reference and DAC. DVDD Digital Supply Voltage, +3.0 V to +5.5 V. DGND Digital Ground. Ground reference point for digital circuitry. CREF1 Reference Capacitor (0.1 µF multilayer ceramic). This external capacitor is used as a charge source for the inter- nal DAC. The capacitor should be tied between the pin and AGND. CREF2 Reference Capacitor (0.01 µF ceramic disc). This external capacitor is used in conjunction with the on-chip refer- ence. The capacitor should be tied between the pin and AGND. AIN1–AIN8 Analog Inputs. Eight analog inputs which can be used as eight single ended inputs (referenced to AGND) or four pseudo differential inputs. Channel configuration is selected by writing to the control register. None of the inputs can go below AGND or above AVDD at any time. See Table III for channel selection. W/B Word/Byte input. When this input is at a logic 1, data is transferred to and from the AD7859/AD7859L in 16-bit words on pins DB0 to DB15. When this pin is at a Logic 0, byte transfer mode is enabled. Data is transferred on pins DB0 to DB7 and pin DB8/HBEN assumes its HBEN functionality. DB0–DB7 Data Bits 0 to 7. Three state data I/O pins that are controlled by CS, RD and WR. Data output is straight binary (unipolar mode) or twos complement (bipolar mode). DB8/HBEN Data Bit 8/High Byte Enable. When W/B is high, this pin acts as Data Bit 7, a three state data I/O pin that is con- trolled by CS, RD and WR. When W/B is low, this pin acts as the High Byte Enable pin. When HBEN is low, then the low byte of data being written to or read from the AD7859/AD7859L is on DB0 to DB7. When HBEN is high, then the high byte of data being written to or read from the AD7859/AD7859L is on DB0 to DB7. DB9–DB15 Data Bits 9 to 15. Three state data I/O pins that are controlled by CS, RD and WR. Data output is straight bi- nary (unipolar mode) or twos complement (bipolar mode). CLKIN Master Clock Signal for the device (4 MHz for AD7859, 1.8 MHz for AD7859L). Sets the conversion and calibra- tion times. CAL Calibration Input. A logic 0 in this pin resets all logic. A rising edge on this pin initiates a calibration. This input overrides all other internal operations. BUSY Busy Output. The busy output is triggered high when a conversion or a calibration is initiated, and remains high until the conversion or calibration is completed. SLEEP Sleep Input. This pin is used in conjunction with the PGMT0 and PGMT1 bits in the control register to deter- mine the power-down mode. Please see the “Power-Down Options” section for details. NC No connect pins. These pins should be left unconnected. REV. A –7–