Datasheet AD9059 (Analog Devices) - 9

AD9059 Digital Logic (5 V/3 V Systems) Applications
The digital inputs and outputs of the AD9059 can easily be The wide analog bandwidth of the AD9059 makes it attractive for configured to interface directly with 3 V or 5 V logic systems. a variety of high performance receiver and encoder applications. The encode and power-down (PWRDN) inputs are CMOS Figure 4 shows the dual ADC in a typical low cost I and Q stages with TTL thresholds of 1.5 V, making the inputs compat- demodulator implementation for cable, satellite, or wireless ible with TTL, 5 V CMOS, and 3 V CMOS logic families. As LAN modem receivers. The excellent dynamic performance of with all high speed data converters, the encode signal should be the ADC at higher analog input frequencies and encode rates clean and jitter free to prevent degradation of ADC dynamic empowers users to employ direct IF sampling techniques (see performance. TPC 2). IF sampling eliminates or simplifies analog mixer and The AD9059’s digital outputs will also interface directly with 5 V filter stages to reduce total system cost and power. or 3 V CMOS logic systems. The voltage supply pins (VDD) for these CMOS stages are isolated from the analog VD voltage
AD9059
supply. By varying the voltage on these supply pins, the digital output high levels will change for 5 V or 3 V systems. The VDD
BPF ADC
pins are internally connected on the AD9059 die. Care should
IF IN 90
° be taken to isolate the VDD supply voltages from the 5 V analog
BPF ADC
supply to minimize noise coupling into the ADCs. The AD9059 provides high impedance digital output operation
VCO VCO
when the ADC is driven into power-down mode (PWRDN, logic high). A 200 ns (minimum) power-down time should be provided before a high impedance characteristic is required. A Figure 4. I and Q Digital Receiver 200 ns power-up period should be provided to ensure accurate The high sampling rate and analog bandwidth of the AD9059 ADC output data after reactivation (valid output data is avail- are ideal for computer RGB video digitizer applications. With a able three clock cycles after the 200 ns delay). full-power analog bandwidth of 2× the maximum sampling rate,
Timing
the ADC provides sufficient pixel-to-pixel transient settling time The AD9059 is guaranteed to operate with conversion rates to ensure accurate 60 MSPS video digitization. Figure 5 shows from 5 MSPS to 60 MSPS. At 60 MSPS, the ADC is designed a typical RGB video digitizer implementation for the AD9059. to operate with an encode duty cycle of 50%, but performance
AD9059
is insensitive to moderate variations. Pulsewidth variations of up
8
to ± 10% (allowing the encode signal to meet the minimum/
RED ADC
maximum high/low specifications) will cause no degradation in
8
ADC performance (see Figure 1).
GREEN ADC
Due to the linked ENCODE architecture of the ADCs, the
PIXEL CLOCK H-SYNC PLL
AD9059 cannot be operated in a 2-channel ping-pong mode.
8 Power Dissipation BLUE ADC
The power dissipation of the AD9059 is specified to reflect a typical application setup under the following conditions: encode
ADC
is 60 MSPS, analog input is –0.5 dBFS at 10.3 MHz, VD is 5 V, V
AD9059
DD is 3 V, and digital outputs are loaded with 7 pF typical (10 pF maximum). The actual dissipation will vary as these conditions are modified in user applications. TPC 7 shows typi- Figure 5. RGB Video Encoder cal power consumption for the AD9059 versus ADC encode frequency and VDD supply voltage. A power-down function allows users to reduce power dissipation when ADC data is not required. A TTL/CMOS high signal (PWRDN) shuts down portions of the dual ADC and brings total power dissipation to less than 10 mW. The internal band gap voltage reference remains active during power-down mode to minimize ADC reactivation time. If the power-down function is not desired, Pin 3 should be tied to ground. Both ADC channels are controlled simultaneously by the PWRDN pin; they cannot be shut down or turned on independently. –8– REV. A Document Outline FEATURES APPLICATIONS PRODUCT DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION SPECIFICATIONS EXPLANATION OF TEST LEVELS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics THEORY OF OPERATION USING THE AD9059 Analog Inputs Voltage Reference Digital Logic (5 V/3 V Systems) Timing Power Dissipation Applications Evaluation Board OUTLINE DIMENSIONS Revision History