Datasheet AD7823 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | 2.7 V to 5.5 V, 4.5 ms, 8-Bit ADC in 8-Lead microSOIC/DIP |
| Páginas / Página | 12 / 8 — AD7823. AC Acquisition Time. VDD. VIN+. RSENSE. VIN–. ADC TRANSFER … |
| Revisión | C |
| Formato / tamaño de archivo | PDF / 186 Kb |
| Idioma del documento | Inglés |
AD7823. AC Acquisition Time. VDD. VIN+. RSENSE. VIN–. ADC TRANSFER FUNCTION. DC Acquisition Time. 111...111. 111...110. 111...000. 011...111
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AD7823
When using the pseudo differential input scheme the signal on For small values of source impedance, the settling time associated VIN– must not vary by more than a 1/2 LSB during the conver- with the sampling circuit (100 ns) is, in effect, the acquisition sion process. If the signal on VIN– varies during conversion, the time of the ADC. For example, with a source impedance (R2) conversion result will be incorrect. For single ended operation, VIN– of 10 Ω, the charge time for the sampling capacitor is approxi- is always connected to AGND. Figure 9 shows the AD7823 pseudo mately 2 ns. The charge time becomes significant for source differential input being used to make a unipolar dc current mea- impedances of 4.6 kΩ and greater. surement. A sense resistor is used to convert the current to a
AC Acquisition Time
voltage, and the voltage is applied to the differential input as In ac applications it is recommended to always buffer analog shown. input signals. The source impedance of the drive circuitry must be kept as low as possible to minimize the acquisition time of
VDD
the ADC. Large values of source impedance will cause the THD to degrade at high throughput rates. In addition, better perfor-
VIN+
mance can generally be achieved by using an external 1 nF
RSENSE AD7823
capacitor on VIN+.
VIN– RL ADC TRANSFER FUNCTION
The output coding of the AD7823 is straight binary. The designed code transitions occur at successive integer LSB values (i.e., Figure 9. DC Current Measurement Scheme 1 LSB, 2 LSBs, etc.). The LSB size is = VREF/256. The ideal trans- fer characteristic for the AD7823 is shown in Figure 11 below.
DC Acquisition Time
The ADC starts a new acquisition phase at the end of a conver- sion and ends on the falling edge of the CONVST signal. At the
111...111
end of a conversion there is a settling time associated with the
111...110
sampling circuit. This settling time lasts approximately 100 ns. The analog signal on VIN+ is also being acquired during this settling time; therefore, the minimum acquisition time needed is approximately 100 ns.
111...000
Figure 10 shows the equivalent charging circuit for the sampling
011...111
capacitor when the ADC is in its acquisition phase. R2 represents
ADC CODE 1LSB = VREF/256
the source impedance of a buffer amplifier or resistive network; R1 is an internal multiplexer resistance and C1 is the sampling capacitor.
000...010 000...001 000...000 R1 V R2 IN+ 125
⍀
0V 1LSB +VREF –1LSB ANALOG INPUT C1 3.5
F
Figure 11. Transfer Characteristic Figure 10. Equivalent Sampling Circuit During the acquisition phase, the sampling capacitor must be charged to within a 1/2 LSB of its final value. The time it takes to charge the sampling capacitor (tCHARGE) is given by the follow- ing formula: tCHARGE = 6.2 × (R2 + 125 Ω) × 3.5 pF REV. C –7–
When using the pseudo differential input scheme the signal on For small values of source impedance, the settling time associated VIN– must not vary by more than a 1/2 LSB during the conver- with the sampling circuit (100 ns) is, in effect, the acquisition sion process. If the signal on VIN– varies during conversion, the time of the ADC. For example, with a source impedance (R2) conversion result will be incorrect. For single ended operation, VIN– of 10 Ω, the charge time for the sampling capacitor is approxi- is always connected to AGND. Figure 9 shows the AD7823 pseudo mately 2 ns. The charge time becomes significant for source differential input being used to make a unipolar dc current mea- impedances of 4.6 kΩ and greater. surement. A sense resistor is used to convert the current to a
AC Acquisition Time
voltage, and the voltage is applied to the differential input as In ac applications it is recommended to always buffer analog shown. input signals. The source impedance of the drive circuitry must be kept as low as possible to minimize the acquisition time of
VDD
the ADC. Large values of source impedance will cause the THD to degrade at high throughput rates. In addition, better perfor-
VIN+
mance can generally be achieved by using an external 1 nF
RSENSE AD7823
capacitor on VIN+.
VIN– RL ADC TRANSFER FUNCTION
The output coding of the AD7823 is straight binary. The designed code transitions occur at successive integer LSB values (i.e., Figure 9. DC Current Measurement Scheme 1 LSB, 2 LSBs, etc.). The LSB size is = VREF/256. The ideal trans- fer characteristic for the AD7823 is shown in Figure 11 below.
DC Acquisition Time
The ADC starts a new acquisition phase at the end of a conver- sion and ends on the falling edge of the CONVST signal. At the
111...111
end of a conversion there is a settling time associated with the
111...110
sampling circuit. This settling time lasts approximately 100 ns. The analog signal on VIN+ is also being acquired during this settling time; therefore, the minimum acquisition time needed is approximately 100 ns.
111...000
Figure 10 shows the equivalent charging circuit for the sampling
011...111
capacitor when the ADC is in its acquisition phase. R2 represents
ADC CODE 1LSB = VREF/256
the source impedance of a buffer amplifier or resistive network; R1 is an internal multiplexer resistance and C1 is the sampling capacitor.
000...010 000...001 000...000 R1 V R2 IN+ 125
⍀
0V 1LSB +VREF –1LSB ANALOG INPUT C1 3.5
F
Figure 11. Transfer Characteristic Figure 10. Equivalent Sampling Circuit During the acquisition phase, the sampling capacitor must be charged to within a 1/2 LSB of its final value. The time it takes to charge the sampling capacitor (tCHARGE) is given by the follow- ing formula: tCHARGE = 6.2 × (R2 + 125 Ω) × 3.5 pF REV. C –7–