Datasheet AD7823 (Analog Devices) - 7

AD7823 CIRCUIT DESCRIPTION SUPPLY 2.7V TO 5.5V TWO-WIRE Converter Operation 10
␮
F 0.1
␮
F SERIAL
The AD7823 is a successive approximation analog-to-digital
INTERFACE
converter based around a charge redistribution DAC. The ADC
V V DD REF
can convert analog input signals in the range 0 V to V
0V TO VREF
DD. Figures
V SCLK IN+ INPUT
4 and 5 below show simplified schematics of the ADC. Figure 4
V AD7823 D
␮
C/
␮
P IN– OUT
shows the ADC during its acquisition phase. SW2 is closed and
AGND CONVST
SW1 is in Position A; the comparator is held in a balanced condi- tion; and the sampling capacitor acquires the signal on VIN+. Figure 6. Typical Connection Diagram
CHARGE Analog Input REDISTRIBUTION DAC
Figure 7 shows an equivalent circuit of the analog input struc-
SAMPLING CAPACITOR
ture of the AD7823. The two diodes, D1 and D2, provide ESD
A VIN+
protection for the analog inputs. Care must be taken to ensure
CONTROL SW1 LOGIC
that the analog input signal never exceeds the supply rails by
B ACQUISITION SW2 PHASE
more than 200 mV. This will cause these diodes to become
COMPARATOR CLOCK
forward biased and start conducting current into the substrate.
VIN– VDD/3 OSC
The maximum current these diodes can conduct without caus- Figure 4. ADC Acquisition Phase ing irreversible damage to the part is 20 mA. The capacitor C2 is typically about 4 pF and can be primarily attributed to pin When the ADC starts a conversion (see Figure 5) SW2 will capacitance. The resistor R1 is a lumped component made up of open, and SW1 will move to Position B causing the comparator the on resistance of a multiplexer and a switch. This resistor is to become unbalanced. The control logic and the charge redis- typically about 125 Ω. The capacitor C1 is the ADC sampling tribution DAC are used to add and subtract fixed amounts of capacitor and has a capacitance of 3.5 pF. charge from the sampling capacitor in order to bring the com- parator back into a balanced condition. When the comparator
VDD
is rebalanced, the conversion is complete. The control logic generates the ADC output code. Figure 11 shows the ADC
D1 C1 R1
transfer function.
3.5pF 125
⍀
VIN+ VDD/3 C2 D2 CHARGE 4pF REDISTRIBUTION CONVERT PHASE – SWITCH OPEN DAC SAMPLING ACQUISITION PHASE – SWITCH CLOSED CAPACITOR A VIN+ CONTROL SW1
Figure 7. Equivalent Analog Input Circuit
LOGIC B CONVERSION SW2 PHASE
The analog input of the AD7823 is made up of a pseudo dif-
COMPARATOR CLOCK
ferential pair, VIN+ pseudo differential with respect to VIN–. The
V V IN– DD/3 OSC
signal is applied to VIN+ but in the pseudo differential scheme the sampling capacitor is connected to V Figure 5. ADC Conversion Phase IN– during conversion— see Figure 8. This input scheme can be used to remove offsets that exist in a system. For example, if a system had an offset of
TYPICAL CONNECTION DIAGRAM
0.5 V, the offset could be applied to V Figure 6 shows a typical connection diagram for the AD7823. IN– and the signal applied to V The serial interface is implemented using two wires; the rising IN+. This has the effect of offsetting the input span by 0.5 V. It is only possible to offset the input span when the reference volt- edge of CONVST enables the serial interface—see Serial age (V Interface section for more details. V REF) is less than VDD – VOFFSET. REF is connected to a well decoupled VDD pin to provide an analog input range of 0 V to VDD. When VDD is first connected, the AD7823 powers up in
CHARGE REDISTRIBUTION
a low current mode, i.e., power-down. A rising edge on the
DAC
CONVST input will cause the part to power up—see Operating
SAMPLING COMPARATOR CAPACITOR
Modes. If power consumption is of concern, the automatic power-
VIN+
down at the end of a conversion should be used to improve
CONTROL VIN(+) LOGIC
power performance. See Power vs. Throughput Rate section of
CONVERSION VOFFSET SW2 PHASE
the data sheet.
VIN– CLOCK VDD/3 OSC VOFFSET
Figure 8. Pseudo Differential Input Scheme –6– REV. C