Datasheet AD7863 (Analog Devices) - 8

AD7863 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DB12 1 28 DB13 DB11 2 27 AGND DB10 3 26 VB1 DB9 4 25 VA1 DB8 5 24 VDD DB7 6 23 BUSY AD7863 DGND 7 22 TOP VIEW RD CONVST 8 (Not to Scale) 21 CS DB6 9 20 A0 DB5 10 19 VREF DB4 11 18 VA2 DB3 12 17 VB2 DB2 13 16 AGND DB1 14 15 DB0
04 0 1- 641 0 Figure 4. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 to 6 DB12 to DB7 Data Bit 12 to Data Bit 7. Three-state TTL outputs. 7 DGND Digital Ground. Ground reference for digital circuitry. 8 CONVST Convert Start Input. Logic input. A high-to-low transition on this input puts both track/holds into their hold mode and starts conversion on both channels. 9 to 15 DB6 to DB0 Data Bit 6 to Data Bit 0. Three-state TTL outputs. 16 AGND Analog Ground. Ground reference for mux, track/hold, reference, and DAC circuitry. 17 VB2 Input Number 2 of Channel B. Analog input voltage ranges of ±10 V (AD7863-10), ±2.5 V (AD7863-3), and 0 V to 2.5 V (AD7863-2). 18 VA2 Input Number 2 of Channel A. Analog input voltage ranges of ±10 V (AD7863-10), ±2.5 V (AD7863-3), and 0 V to 2.5 V (AD7863-2). 19 VREF Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the output reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V, and this appears at the pin. 20 A0 Multiplexer Select. This input is used in conjunction with CONVST to determine on which pair of channels the conversion is to be performed. If A0 is low when the conversion is initiated, then channels VA1 and VA2 are selected. If A0 is high when the conversion is initiated, channels VB1 and VB2 are selected. 21 CS Chip Select Input. Active low logic input. The device is selected when this input is active. 22 RD Read Input. Active low logic input. This input is used in conjunction with CS low to enable the data outputs and read a conversion result from the AD7863. 23 BUSY Busy Output. The busy output is triggered high by the falling edge of CONVST and remains high until conversion is completed. 24 VDD Analog and Digital Positive Supply Voltage, 5.0 V ± 5%. 25 VA1 Input Number 1 of Channel A. Analog input voltage ranges of ±10 V (AD7863-10), ±2.5 V (AD7863-3), and 0 V to 2.5 V (AD7863-2). 26 VB1 Input Number 1 of Channel B. Analog input voltage ranges of ±10 V (AD7863-10), ±2.5 V (AD7863-3), and 0 V to 2.5 V (AD7863-2). 27 AGND Analog Ground. Ground reference for mux, track/hold, reference, and DAC circuitry. 28 DB13 Data Bit 13 (MSB). Three-state TTL output. Output coding is twos complement for the AD7863-10 and AD7863-3. Output coding is straight (natural) binary for the AD7863-2. Rev. B | Page 7 of 24 Document Outline FEATURES GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY CONVERTER DETAILS TRACK-AND-HOLD SECTION REFERENCE SECTION CIRCUIT DESCRIPTION ANALOG INPUT SECTION OFFSET AND FULL-SCALE ADJUSTMENT Positive Full-Scale Adjust (−10 Version) Negative Full-Scale Adjust (−10 Version) TIMING AND CONTROL Read Options OPERATING MODES MODE 1 OPERATION Normal Power, High Sampling Performance MODE 2 OPERATION Power-Down, Auto-Sleep After Conversion AD7863 DYNAMIC SPECIFICATIONS SIGNAL-TO-NOISE RATIO (SNR) EFFECTIVE NUMBER OF BITS TOTAL HARMONIC DISTORTION (THD) INTERMODULATION DISTORTION PEAK HARMONIC OR SPURIOUS NOISE DC LINEARITY PLOT POWER CONSIDERATIONS MICROPROCESSOR INTERFACING AD7863 TO ADSP-2100 INTERFACE AD7863 TO ADSP-2101/ADSP-2102 INTERFACE AD7863 TO TMS32010 INTERFACE AD7863 TO TMS320C25 INTERFACE AD7863 TO MC68000 INTERFACE AD7863 TO 80C196 INTERFACE VECTOR MOTOR CONTROL MULTIPLE AD7863S APPLICATIONS HINTS PC BOARD LAYOUT CONSIDERATIONS GROUND PLANES POWER PLANES SUPPLY DECOUPLING OUTLINE DIMENSIONS ORDERING GUIDE