Datasheet AD7888 (Analog Devices) - 9

AD7888
Figure 4 shows the typical power supply rejection ratio vs.
CHARGE
frequency for the part. The power supply rejection ratio is defined
REDISTRIBUTION DAC
as the ratio of the power in the ADC output at frequency f
SAMPLING
to the power of a full-scale sine wave applied to the ADC of
CAPACITOR A
frequency fs:
AIN CONTROL SW1 B LOGIC
PSRR (dB) = 10 log (Pf/Pfs)
ACQUISITION AGND PHASE SW2 COMPARATOR
Pf = Power at frequency f in ADC output, Pfs = power at fre- quency fs in ADC full scale input. Here a 100 mV peak-to-peak
(REF IN/REF OUT)/2
sine wave is coupled onto the VDD supply. Both the 2.7 V and 5.5 V supply performances are shown. Figure 5. ADC Acquisition Phase When the ADC starts a conversion, (see Figure 6), SW2 will open
–75
and SW1 will move to Position B causing the comparator to
VDD = 5.5V/2.7V
become unbalanced. The control logic and the charge redistribu-
–77 100mV p-p SINE WAVE ON VDD
tion DAC are used to add and subtract fixed amounts of charge
REFIN = 2.488V EXT REFERENCE –79
from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the
–81
conversion is complete. The control logic generates the ADC
dB – –83
output code. Figure 7 shows the ADC transfer function.
–85 PSRR –87 CHARGE REDISTRIBUTION DAC –89 SAMPLING CAPACITOR –91 A VIN CONTROL SW1 –93 LOGIC B 2.65 12.85 23.15 33.65 43.85 54.35 64.15 CONVERSION PHASE INPUT FREQUENCY – kHz AGND SW2 COMPARATOR
Figure 4. PSRR vs. Frequency
(REF IN/REF OUT)/2 CIRCUIT INFORMATION
Figure 6. ADC Conversion Phase The AD7888 is a fast, low power, 12-bit, single supply, 8-channel A/D converter. The part can be operated from 3 V (2.7 V to
ADC TRANSFER FUNCTION
3.6 V) supply or from 5 V (4.75 V to 5.25 V) supply. When The output coding of the AD7888 is straight binary. The operated from either a 5 V supply or a 3 V supply, the AD7888 designed code transitions occur at successive integer LSB is capable of throughput rates of 125 kSPS when provided with values (i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = VREF/ a 2 MHz clock. 4096. The ideal transfer characteristic for the AD7888 is shown in Figure 7 below. The AD7888 provides the user with an 8-channel multiplexer, on-chip track/hold, A/D converter, reference and serial interface housed in a tiny 16-lead TSSOP package, which offers the user considerable space saving advantages over alternative solutions.
111...111
The serial clock input accesses data from the part and also
111...110
provides the clock source for the successive-approximation A/D converter. The analog input range is 0 to VREF (where
111...000
the externally-applied VREF can be between 1.2 V and VDD).
1LSB = VREF/4096
The 8-channel multiplexer is controlled by the part’s Control
ADC CODE 011...111
Register. This Control Register also allows the user to power-off the internal reference and to determine the Modes of Operation.
000...010 000...001 CONVERTER OPERATION 000...000 0.5LSB +VREF – 1.5LSB
The AD7888 is a successive-approximation analog-to-digital
0V ANALOG INPUT
converter based around a charge redistribution DAC. Figures 5 and 6 show simplified schematics of the ADC. Figure 5 shows Figure 7. Transfer Characteristic the ADC during its acquisition phase. SW2 is closed and SW1 is in Position A, the comparator is held in a balanced condition and the sampling capacitor acquires the signal on AIN. –8– REV. C