Datasheet AD9214 (Analog Devices) - 8

FabricanteAnalog Devices
Descripción10-Bit, 65/80/105 MSPS, +3.3V A/D Converter
Páginas / Página21 / 8 — AD9214. TERMINOLOGY. Harmonic Distortion, Third. Analog Bandwidth. …
RevisiónD
Formato / tamaño de archivoPDF / 486 Kb
Idioma del documentoInglés

AD9214. TERMINOLOGY. Harmonic Distortion, Third. Analog Bandwidth. Integral Nonlinearity. Aperture Delay. Minimum Conversion Rate

AD9214 TERMINOLOGY Harmonic Distortion, Third Analog Bandwidth Integral Nonlinearity Aperture Delay Minimum Conversion Rate

Línea de modelo para esta hoja de datos

Versión de texto del documento

AD9214 TERMINOLOGY Harmonic Distortion, Third Analog Bandwidth
The ratio of the rms signal amplitude to the rms value of the The analog input frequency at which the spectral power of the third harmonic component, reported in dBc. fundamental frequency (as determined by the FFT analysis) is
Integral Nonlinearity
reduced by 3 dB. The deviation of the transfer function from a reference line
Aperture Delay
measured in fractions of 1 LSB using a “best straight line” The delay between the 50% point of the rising edge of the determined by a least square curve fit. ENCODE command and the instant at which the analog input
Minimum Conversion Rate
is sampled. The encode rate at which the SNR of the lowest analog signal
Aperture Uncertainty (Jitter)
frequency drops by no more than 3 dB below the guaranteed limit. The sample-to-sample variation in aperture delay.
Maximum Conversion Rate Differential Analog Input Resistance, Differential Analog
The encode rate at which parametric testing is performed.
Input Capacitance and Differential Analog Input Impedance Output Propagation Delay
The real and complex impedances measured at each analog The delay between a differential crossing of ENCODE and input port. The resistance is measured statically and the capaci- ENCODE and the time when all output data bits are within tance and differential input impedances are measured with a valid logic levels. network analyzer. Noise (for any range within the ADC)
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to FSdBm SNRdBc Signal the converter to generate a full-scale response. Peak differen- V dBFS = × 0 001 . × − − NOISE Z 10 10 tial voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is Where Z is the input impedance, FS is the full-scale of the 180 degrees out of phase. Peak-to-peak differential is computed device for the frequency in question, SNR is the value for the by rotating the inputs phase 180 degrees and taking the peak particular input level and Signal is the signal level within the measurement again. Then the difference is computed between ADC reported in dB below full-scale. This value includes both both peak measurements. thermal and quantization noise.
Differential Nonlinearity Power Supply Rejection Ratio (PSRR)
The deviation of any code width from an ideal 1 LSB step. The ratio of a change in input offset voltage to a change in
Effective Number of Bits
power supply voltage. The effective number of bits (ENOB) is calculated from the
Signal-to-Noise-and-Distortion (SINAD)
measured SNR based on the equation: The ratio of the rms signal amplitude (set 0.5 dB below full scale) to the rms value of the sum of all other spectral compo- Full Scale  SINAD – . 1 76 +  nents, including harmonics but excluding dc. MEASURED dB 20 log  Actual  ENOB =
Signal-to-Noise Ratio (without Harmonics)
. 6 02 The ratio of the rms signal amplitude (set at 0.5 dB below full scale) to the rms value of the sum of all other spectral compo-
Encode Pulsewidth/Duty Cycle
nents, excluding the first five harmonics and dc. Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in Logic “1” state to achieve rated performance;
Spurious-Free Dynamic Range (SFDR)
pulsewidth low is the minimum time ENCODE pulse should be left The ratio of the rms signal amplitude to the rms value of the in low state. See timing implications of changing t peak spurious spectral component. The peak spurious compo- ENCH in text. At a given clock rate, these specs define an acceptable Encode duty cycle. nent may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered), or dBFS (always
Full-Scale Input Power
related back to converter full scale). Expressed in dBm. Computed using the following equation:
Two-Tone Intermodulation Distortion Rejection
V 2  The ratio of the rms value of either input tone to the rms value FULL SCALE rms  of the worst third order intermodulation product; reported in dBc. Z  Power INPUT = FULL SCALE 10 log    0 001 . 
Two-Tone SFDR
  The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an intermodulation distortion product. May
Gain Error
be reported in dBc (i.e., degrades as signal level is lowered), or Gain error is the difference between the measured and ideal full in dBFS (always related back to converter full scale). scale input voltage range of the ADC.
Worst Other Spur Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third second harmonic component, reported in dBc. harmonic) reported in dBc. REV. D –7–