Datasheet AD9214 (Analog Devices) - 7

AD9214 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function
1 OR CMOS Output; Out-of-Range Indicator. Logic HIGH indicates the analog input voltage was outside the converter’s range for the current output data. 2 DFS/GAIN Data Format Select and Gain Mode Select. Connect externally to AVDD for two’s complement data format and 1 V p-p analog input range. Connect externally to AGND for Offset Binary data format and 1 V p-p analog input range. Connect externally to REF (Pin 4) for two’s complement data format and 2 V p-p analog input range. Floating this pin will configure the device for Offset Binary data format and a 2 V p-p analog input range. 3 REFSENSE Reference Mode Select Pin for the ADC. This pin is normally connected externally to AGND, which enables the internal 1.25 V reference, and configures REF (Pin 4) as an analog reference output pin. Connecting REFSENSE externally to AVDD disables the internal reference, and config- ures REF (Pin 4) as an external reference input. In this case, the user must drive REF with a clean and accurate 1.25 V (± 5%) reference input. 4 REF Reference input or output as configured by REFSENSE (Pin 3). When configured as an output (REFSENSE = AGND), the internal reference (nominally 1.25 V) is enabled and is available to the user on this pin. When configured as an input (REFSENSE = AVDD), the user must drive REF with a clean and accurate 1.25 V (± 5%) reference. This pin should be bypassed to AGND with an external 0.1 µF capacitor, whether it is configured as an input or output. 5, 8, 11 AGND Analog Ground 6, 7, 12 AVDD Analog Power Supply, Nominally 3 V 9 AIN Positive terminal of the differential analog input for the ADC. 10 AIN Negative terminal of the differential analog input for the ADC. This pin can be left open if operating in single-ended mode, but it is preferable to match the impedance seen at the positive terminal (see Driving the Analog Inputs). 13 ENCODE Encode Clock for the ADC. The AD9214 samples the analog signal on the rising edge of ENCODE. 14 PWRDN CMOS-compatible power-down mode select, Logic LOW for normal operation; Logic HIGH for power-down mode (digital outputs in high impedance state). PWRDN has an internal 10 kΩ pull-down resistor to ground. 15, 23 DGND Digital Output Ground 16, 24 DrVDD Digital Output Driver Power Supply. Nominally 2.5 V to 3.6 V. 17–22, 25–28 D0 (LSB)–D5, CMOS Digital Outputs of ADC D6–D9 (MSB)
PIN CONFIGURATION 28-Lead Shrink Small Outline Package OR 1 28 D9 (MSB) DFS/GAIN 2 27 D8 REFSENSE 3 26 D7 REF 4 25 D6 AGND 5 24 DrVDD AV 6 23 DD DGND AD9214 AV 7 DD TOP VIEW 22 D5 (Not to Scale) AGND 8 21 D4 A 9 IN 20 D3 A 10 19 IN D2 AGND 11 18 D1 AV 12 17 DD D0 (LSB) ENCODE 13 16 DrVDD PWRDN 14 15 DGND
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