Datasheet AD9410 (Analog Devices)

10-Bit, 210 MSPS ADC AD9410 FEATURES FUNCTIONAL BLOCK DIAGRAM REF V SNR = 54 dB with 99 MHz analog input IN REFOUT AGND DGND D VDD VCC 500 MHz analog bandwidth On-chip reference and track and hold AD9410 REFERENCE OR 1.5 V p-p differential analog input range 10 A PORT DA9–DA0 5.0 V and 3.3 V supply operation A 3.3 V CMOS/TTL outputs AIN ADC 10 T/H 10-BIT Power: 2.1 W typical at 210 MSPS AIN CORE ORB 10 Demultiplexed outputs each at 105 MSPS PORT DB9–DB0 DS B Output data format option DS TIMING AND Data sync input and data clock output provided CLK+ SYNCHRONIZATION CLK– Interleaved or parallel data output option DCO DCO
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APPLICATIONS DFS I/P
016 Figure 1.
Communications and radars Local multipoint distribution services (LMDS) High-end imaging systems and projectors Cable reverse paths Point-to-point radio links GENERAL DESCRIPTION
The AD9410 is a 10-bit monolithic sampling analog-to-digital Fabricated on an advanced BiCMOS process, the AD9410 is converter (ADC) with an on-chip track-and-hold circuit and is available in an 80-lead thin quad flat package, exposed pad optimized for high speed conversion and ease of use. The product specified over the industrial temperature range (−40°C to +85°C). operates at a 210 MSPS conversion rate, with outstanding
PRODUCT HIGHLIGHTS
dynamic performance over its full operating range. 1. High Resolution at High Speed—The architecture is spe- The ADC requires a 5.0 V and 3.3 V power supply and up to a cifically designed to support conversion up to 210 MSPS 210 MHz differential clock input for full performance operation. with outstanding dynamic performance. No external reference or driver components are required for many applications. The digital outputs are TTL-/CMOS-compatible and 2. Demultiplexed Output—Output data is decimated by two separate output power supply pins also support interfacing with and provided on two data ports for ease of data transport. 3.3 V logic. 3. Output Data Clock—The AD9410 provides an output data The clock input is differential and TTL-/CMOS-compatible. clock synchronous with the output data, simplifying the The 10-bit digital outputs can be operated from 3.3 V (2.5 V to timing between data and other logic. 3.6 V) supplies. Two output buses support demultiplexed data 4. Data Synchronization—A DS input is provided to allow for up to 105 MSPS rates and binary or twos complement output synchronization of two or more AD9410s in a system, or to coding format is available. A data sync function is provided for synchronize data to a specific output port in a single timing-dependent applications. An output clock simplifies AD9410 system. interfacing to external logic. The output data bus timing is selectable for parallel or interleaved mode, allowing for flexibility in latching output data.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS SWITCHING SPECIFICATIONS DIGITAL SPECIFICATIONS AC SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLAINATION OF TEST LEVELS Test Level ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY EQUIVALENT CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION USING THE AD9410 Clock Input ANALOG INPUT DIGITAL OUTPUTS CLOCK OUTPUTS (DCO, ) VOLTAGE REFERENCE TIMING DATA SYNC (DS) OUTLINE DIMENSIONS ORDERING GUIDE