Datasheet AD7492 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | 1MSPS, 4mW Internal Ref & Clk, 12-Bit Parallel ADC |
| Páginas / Página | 25 / 7 — AD7492. TIMING SPECIFICATIONS. Table 3. Limit. TMIN, TMAX. Parameter. … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 377 Kb |
| Idioma del documento | Inglés |
AD7492. TIMING SPECIFICATIONS. Table 3. Limit. TMIN, TMAX. Parameter. AD7492/AD7492-4. AD7492-52. Unit. Description. 200µA. IOL. TO OUTPUT
Línea de modelo para esta hoja de datos
Versión de texto del documento
link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7 link to page 7
AD7492 TIMING SPECIFICATIONS
VDD = 2.7 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.1
Table 3. Limit at TMIN, TMAX Parameter AD7492/AD7492-4 AD7492-52 Unit Description
tCONVERT 880 680 ns max tWAKEUP 203 203 μs max Partial Sleep Wake-Up Time 500 500 μs max Full Sleep Wake-Up Time t1 10 10 ns min CONVST Pulse Width t2 10 10 ns max CONVST to BUSY Delay, VDD = 5 V 40 N/A ns max CONVST to BUSY Delay, VDD = 3 V t3 0 0 ns max BUSY to CS Setup Time t 4 4 0 0 ns max CS to RD Setup Time t5 20 20 ns min RD Pulse Width t 4 6 15 15 ns min Data Access Time after Falling Edge of RD t 5 7 8 8 ns max Bus Relinquish Time after Rising Edge of RD t8 0 0 ns max CS to RD Hold Time t9 120 120 ns min Acquisition Time t10 100 100 ns min Quiet Time 1 Sample tested @ 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V (see Figure 2). 2 The AD7492-5 is specified with VDD = 4.75 V to 5.25 V. 3 This is the time needed for the part to settle within 0.5 LSB of its stable value. Conversion can be initiated earlier than 20 μs, but there is no guarantee that the part samples within 0.5 LSB of the true analog input value. Therefore, the user should not start conversion until after the specified time. 4 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V 5 t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t7, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
200µA IOL TO OUTPUT 1.6V PIN CL 50pF
02
200µA I
0
OH
28- 11 0 Figure 2. Load Circuit for Digital Output Timing Specifications Rev. A | Page 6 of 24 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7492-5 AD7492/AD7492-4 TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PEFORMANCE CHARACTERISTICS TERMINOLOGY CIRCUIT DESCRIPTION CONVERTER OPERATION TYPICAL CONNECTION DIAGRAM ADC TRANSFER FUNCTION AC ACQUISITION TIME DC ACQUISITION TIME ANALOG INPUT PARALLEL INTERFACE OPERATING MODES POWER-UP GROUNDING AND LAYOUT POWER SUPPLIES MICROPROCESSOR INTERFACING OUTLINE DIMENSIONS ORDERING GUIDE
AD7492 TIMING SPECIFICATIONS
VDD = 2.7 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.1
Table 3. Limit at TMIN, TMAX Parameter AD7492/AD7492-4 AD7492-52 Unit Description
tCONVERT 880 680 ns max tWAKEUP 203 203 μs max Partial Sleep Wake-Up Time 500 500 μs max Full Sleep Wake-Up Time t1 10 10 ns min CONVST Pulse Width t2 10 10 ns max CONVST to BUSY Delay, VDD = 5 V 40 N/A ns max CONVST to BUSY Delay, VDD = 3 V t3 0 0 ns max BUSY to CS Setup Time t 4 4 0 0 ns max CS to RD Setup Time t5 20 20 ns min RD Pulse Width t 4 6 15 15 ns min Data Access Time after Falling Edge of RD t 5 7 8 8 ns max Bus Relinquish Time after Rising Edge of RD t8 0 0 ns max CS to RD Hold Time t9 120 120 ns min Acquisition Time t10 100 100 ns min Quiet Time 1 Sample tested @ 25°C to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V (see Figure 2). 2 The AD7492-5 is specified with VDD = 4.75 V to 5.25 V. 3 This is the time needed for the part to settle within 0.5 LSB of its stable value. Conversion can be initiated earlier than 20 μs, but there is no guarantee that the part samples within 0.5 LSB of the true analog input value. Therefore, the user should not start conversion until after the specified time. 4 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V 5 t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t7, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
200µA IOL TO OUTPUT 1.6V PIN CL 50pF
02
200µA I
0
OH
28- 11 0 Figure 2. Load Circuit for Digital Output Timing Specifications Rev. A | Page 6 of 24 Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7492-5 AD7492/AD7492-4 TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PEFORMANCE CHARACTERISTICS TERMINOLOGY CIRCUIT DESCRIPTION CONVERTER OPERATION TYPICAL CONNECTION DIAGRAM ADC TRANSFER FUNCTION AC ACQUISITION TIME DC ACQUISITION TIME ANALOG INPUT PARALLEL INTERFACE OPERATING MODES POWER-UP GROUNDING AND LAYOUT POWER SUPPLIES MICROPROCESSOR INTERFACING OUTLINE DIMENSIONS ORDERING GUIDE