Datasheet AD7492 (Analog Devices)

1.25 MSPS, 16 mW Internal REF and CLK, 12-Bit Parallel ADC AD7492 FEATURES FUNCTIONAL BLOCK DIAGRAM Specified for VDD of 2.7 V to 5.25 V AVDD DVDD REF OUT VDRIVE Throughput rate of 1 MSPS (AD7492) 4 20 5 21 Throughput rate of 1.25 MSPS (AD7492-5) 2.5V REF CLOCK Throughput rate of 400 kSPS (AD7492-4) OSCILLATOR BUF Low power 4 mW typ at 1 MSPS with 3 V supplies 11 mW typ at 1 MSPS with 5 V supplies DB11 V 6 12-BIT SAR IN T/H OUTPUT DRIVERS Wide input bandwidth ADC DB0 70 dB typ SNR at 100 kHz input frequency 2.5 V internal reference On-chip CLK oscillator 11 PS/FS CONTROL Flexible power/throughput rate management CONVST 10 8 CS LOGIC No pipeline delays 9 RD AD7492 High speed parallel interface 12 BUSY Sleep mode: 50 nA typ 7 19 24-lead SOIC and TSSOP packages
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AGND DGND
011 Figure 1.
GENERAL DESCRIPTION
The AD7492, AD7492-4, and AD7492-5 are 12-bit high speed, The type of sleep mode is hardware selected by the PS/FS pin. low power, successive approximation ADCs. The parts operate Using these sleep modes allows very low power dissipation from a single 2.7 V to 5.25 V power supply and feature numbers at lower throughput rates. throughput rates up to 1.25 MSPS. They contain a low noise, wide bandwidth track/hold amplifier that can handle The analog input range for the part is 0 V to REFIN. The bandwidths up to 10 MHz. 2.5 V reference is supplied internally and is available for external referencing. The conversion rate is determined by the The conversion process and data acquisition are controlled internal clock. using standard control inputs allowing for easy interface to microprocessors or DSPs. The input signal is sampled on the
PRODUCT HIGHLIGHTS
falling edge of CONVST and conversion is also initiated at this 1. High Throughput with Low Power Consumption. The point. The BUSY pin goes high at the start of conversion and AD7492-5 offers 1.25 MSPS throughput with 16 mW goes low 880 ns (AD7492/AD7492-4) or 680 ns (AD7492-5) power consumption. later to indicate that the conversion is complete. There are no 2. Flexible Power/Throughput Rate Management. The pipeline delays associated with the part. The conversion result is conversion time is determined by an internal clock. The accessed via standard CS and RD signals over a high speed part also features two sleep modes, partial and full, to parallel interface. maximize power efficiency at lower throughput rates. The AD7492 uses advanced design techniques to achieve very 3. No Pipeline Delay. The part features a standard successive low power dissipation at high throughput rates. With 5 V approximation ADC with accurate control of the sampling supplies and 1.25 MSPS, the average current consumption instant via a CONVST input and once-off conversion AD7492-5 is typically 2.75 mA. The part also offers flexible control. power/throughput rate management. 4. Flexible Digital Interface. The VDRIVE feature controls the It is also possible to operate the part in a full sleep mode and a voltage levels on the I/O digital pins. partial sleep mode, where the part wakes up to do a conversion 5. Fewer Peripheral Components. The AD7492 optimizes and automatically enters a sleep mode at the end of conversion. PCB space by using an internal reference and internal CLK.
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Document Outline FEATURES FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS AD7492-5 AD7492/AD7492-4 TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PEFORMANCE CHARACTERISTICS TERMINOLOGY CIRCUIT DESCRIPTION CONVERTER OPERATION TYPICAL CONNECTION DIAGRAM ADC TRANSFER FUNCTION AC ACQUISITION TIME DC ACQUISITION TIME ANALOG INPUT PARALLEL INTERFACE OPERATING MODES POWER-UP GROUNDING AND LAYOUT POWER SUPPLIES MICROPROCESSOR INTERFACING OUTLINE DIMENSIONS ORDERING GUIDE