Datasheet AD9244 (Analog Devices) - 10

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AD9244 TERMINOLOGY Analog Bandwidth (Full Power Bandwidth) IF Sampling
The analog input frequency at which the spectral power of the Due to the effects of aliasing, an ADC is not necessarily limited fundamental frequency (as determined by the FFT analysis) is to Nyquist sampling. Higher sampled frequencies are aliased reduced by 3 dB. down into the first Nyquist zone (DC − fCLOCK/2) on the output of the ADC. Care must be taken that the bandwidth of the sam-
Aperture Delay
pled signal does not overlap Nyquist zones and alias onto itself. The delay between the 50% point of the rising edge of the clock Nyquist sampling performance is limited by the bandwidth of and the instant at which the analog input is sampled. the input SHA and clock jitter (noise caused by jitter increases
Aperture Uncertainty (Jitter)
as the input frequency increases). The sample-to-sample variation in aperture delay.
Integral Nonlinearity (INL) Differential Analog Input Voltage Range
INL refers to the deviation of each individual code from a line The peak-to-peak differential voltage must be applied to the drawn from negative full scale through positive full scale. The converter to generate a full-scale response. Peak differential point used as negative full scale occurs ½ LSB before the first voltage is computed by observing the voltage on a single pin code transition. Positive full scale is defined as a level 1½ LSB and subtracting the voltage from the other pin, which is 180° beyond the last code transition. The deviation is measured from out of phase. Peak-to-peak differential is computed by rotating the middle of each particular code to the true straight line. the input phase 180° and taking the peak measurement again. The
Minimum Conversion Rate
difference is then found between the two peak measurements. The clock rate at which the SNR of the lowest analog signal
Differential Nonlinearity (DNL, No Missing Codes)
frequency drops by no more than 3 dB below the guaranteed limit. An ideal ADC exhibits code transitions that are exactly 1 LSB
Maximum Conversion Rate
apart. DNL is the deviation from this ideal value. Guaranteed The clock rate at which parametric testing is performed. no missing codes to 14-bit resolution indicates that all 16,384 codes must be present over all operating ranges.
Nyquist Sampling
When the frequency components of the analog input are below
Dual-Tone SFDR
1 the Nyquist frequency (fCLOCK/2). The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component
Out-of-Range Recovery Time
may or may not be an IMD product. The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive full scale to 10%
Effective Number of Bits (ENOB)
above negative full scale, or from 10% below negative full scale The ENOB for a device for sine wave inputs at a given input to 10% below positive full scale. frequency can be calculated directly from its measured SINAD by N = (SINAD − 1.76)/6.02
Power Supply Rejection Ratio (PSRR)
The change in full scale from the value with the supply at its
Gain Error
minimum limit to the value with the supply at its maximum limit. The first code transition should occur at an analog value ½ LSB above negative full scale. The last code transition should occur
Signal-to-Noise-and-Distortion (SINAD)1
at an analog value 1½ LSB below the nominal full scale. Gain The ratio of the rms signal amplitude to the rms value of the T error is the deviation of the actual difference between first and sum of all other spectral components below the Nyquist last code transitions and the ideal difference between first and frequency, including harmonics, but excluding dc. last code transitions.
Signal-to-Noise Ratio (SNR)1 Common-Mode Rejection Ratio (CMRR)
The ratio of the rms signal amplitude to the rms value of the Common-mode (CM) signals appearing on VIN+ and VIN– sum of all other spectral components below the Nyquist are ideally rejected by the differential front end of the ADC. frequency, excluding the first six harmonics and dc. With a full-scale CM signal driving both VIN+ and VIN–, CMRR is the ratio of the amplitude of the full-scale input CM signal to the amplitude of signal that is not rejected, expressed in dBFS.1 Rev. C | Page 9 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL APPLICATION CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW ANALOG INPUT OPERATION Single-Ended Input Configuration Differentially Driving the Analog Inputs REFERENCE OPERATION Pin-Programmable Reference Resistor-Programmable Reference Using an External Reference Digital Outputs Data Format Select (DFS) Digital Output Driver Considerations DIGITAL INPUTS AND OUTPUTS Out of Range (OTR) Digital Output Enable Function (OEB) Clock Overview Clock Input Modes Clock Input Considerations Clock Power Dissipation Clock Stabilizer (DCS) Grounding and Decoupling Analog and Digital Grounding Analog Supply Decoupling Digital Supply Decoupling Reference Decoupling CML VR EVALUATION BOARD ANALOG INPUT CONFIGURATION REFERENCE CONFIGURATION CLOCK CONFIGURATION OUTLINE DIMENSIONS ORDERING GUIDE