Datasheet AD9244 (Analog Devices) - 5

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AD9244 AC SPECIFICATIONS
AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS (–65) or 40 MSPS (–40), differential clock inputs, VREF = 2 V, external reference, AIN = –0.5 dBFS, differential analog inputs, unless otherwise noted.
Table 2. Test AD9244BST-65 AD9244BST-40 Parameter Temp Level Min Typ Max Min Typ Max Unit
SNR1 fIN = 2.4 MHz Full VI 72.4 73.4 dBc 25°C I 74.8 75.3 dBc fIN = 15.5 MHz (–1 dBFS) Full IV 72.0 dBc 25°C V 73.7 dBc fIN = 20 MHz Full VI 72.1 dBc 25°C I 74.7 dBc fIN = 32.5 MHz Full IV 70.8 dBc 25°C I 73.0 dBc fIN = 70 MHz Full IV 69.9 dBc 25°C V 72.2 dBc fIN = 100 MHz 25°C V 71.2 72.8 dBc fIN = 200 MHz 25°C V 67.2 68.3 dBc SINAD1 fIN = 2.4 MHz Full VI 72.2 73.2 dBc 25°C I 74.7 75.1 dBc fIN = 20 MHz Full VI 72 dBc 25°C I 74.4 dBc fIN = 32.5 MHz Full IV 70.6 dBc 25°C I 72.6 dBc fIN = 70 MHz Full IV 69.7 dBc 25°C V 71.9 dBc fIN = 100 MHz 25°C V 71 72.4 dBc fIN = 200 MHz 25°C V 59.8 56.3 dBc ENOB fIN = 2.4 MHz Full VI 11.7 11.9 Bits 25°C I 12.1 12.2 Bits fIN = 20 MHz Full VI 11.7 Bits 25°C I 12.1 Bits fIN = 32.5 MHz Full IV 11.4 Bits 25°C I 11.8 Bits fIN = 70 MHz Full IV 11.3 Bits 25°C V 11.7 Bits fIN = 100 MHz 25°C V 11.5 11.7 Bits fIN = 200 MHz 25°C V 9.6 9.1 Bits THD1 fIN = 2.4 MHz Full VI −78.4 −80.7 dBc 25°C I −90.0 −89.7 dBc fIN = 20 MHz Full VI −80.4 dBc 25°C I −89.4 dBc fIN = 32.5 MHz Full IV −79.2 dBc 25°C I −84.6 dBc fIN = 70 MHz Full IV −78.7 dBc 25°C V −84.1 dBc fIN = 100 MHz 25°C V −83.0 −83.2 dBc fIN = 200 MHz 25°C V −60.7 −56.6 dBc Rev. C | Page 4 of 36 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL APPLICATION CIRCUITS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG INPUT AND REFERENCE OVERVIEW ANALOG INPUT OPERATION Single-Ended Input Configuration Differentially Driving the Analog Inputs REFERENCE OPERATION Pin-Programmable Reference Resistor-Programmable Reference Using an External Reference Digital Outputs Data Format Select (DFS) Digital Output Driver Considerations DIGITAL INPUTS AND OUTPUTS Out of Range (OTR) Digital Output Enable Function (OEB) Clock Overview Clock Input Modes Clock Input Considerations Clock Power Dissipation Clock Stabilizer (DCS) Grounding and Decoupling Analog and Digital Grounding Analog Supply Decoupling Digital Supply Decoupling Reference Decoupling CML VR EVALUATION BOARD ANALOG INPUT CONFIGURATION REFERENCE CONFIGURATION CLOCK CONFIGURATION OUTLINE DIMENSIONS ORDERING GUIDE