Datasheet AD9236 (Analog Devices) - 9

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AD9236 Data Sheet TERMINOLOGY Analog Bandwidth (Full Power Bandwidth) Signal-to-Noise and Distortion (SINAD)1
The analog input frequency at which the spectral power of the The ratio of the rms input signal amplitude to the rms value of fundamental frequency (as determined by the FFT analysis) is the sum of all other spectral components below the Nyquist reduced by 3 dB. frequency, including harmonics but excluding dc.
Aperture Delay (tA) Effective Number of Bits (ENOB)
The delay between the 50% point of the rising edge of the clock The effective number of bits for a sine wave input at a given and the instant at which the analog input is sampled. input frequency can be calculated directly from its measured SINAD using the following formula
Aperture Uncertainty (Jitter, tJ)
The sample-to-sample variation in aperture delay. ( −1.76) = SINAD ENOB 6.02
Integral Nonlinearity (INL)
The deviation of each individual code from a line drawn from
Signal-to-Noise Ratio (SNR)1
negative full scale through positive full scale. The point used as The ratio of the rms input signal amplitude to the rms value of negative full scale occurs ½ LSB before the first code transition. the sum of all other spectral components below the Nyquist Positive full scale is defined as a level 1½ LSB beyond the last frequency, excluding the first six harmonics and dc. code transition. The deviation is measured from the middle of
Spurious Free Dynamic Range (SFDR)1
each particular code to the true straight line. The difference in dB between the rms input signal amplitude
Differential Nonlinearity (DNL, No Missing Codes)
and the peak spurious signal. The peak spurious component An ideal ADC exhibits code transitions that are exactly 1 LSB may or may not be a harmonic. apart. DNL is the deviation from this ideal value. Guaranteed
Two-Tone SFDR1
no missing codes to 12-bit resolution indicates that al 4096 The ratio of the rms value of either input tone to the rms value codes must be present over al operating ranges. of the peak spurious component. The peak spurious component
Offset Error
may or may not be an IMD product. The major carry transition should occur for an analog value
Clock Pulse Width and Duty Cycle
½ LSB below VIN+ = VIN–. Offset error is defined as the deviation Pulse width high is the minimum amount of time that the clock of the actual transition from that point. pulse should be left in the Logic 1 state to achieve rated
Gain Error
performance. Pulse width low is the minimum time the clock The first code transition should occur at an analog value pulse should be left in the low state. At a given clock rate, these ½ LSB above negative full scale. The last transition should occur specifications define an acceptable clock duty cycle. at an analog value 1½ LSB below positive full scale. Gain error
Minimum Conversion Rate
is the deviation of the actual difference between first and last The clock rate at which the SNR of the lowest analog signal code transitions and the ideal difference between first and last frequency drops by no more than 3 dB below the guaranteed limit. code transitions.
Maximum Conversion Rate Temperature Drift
The clock rate at which parametric testing is performed. The temperature drift for offset error and gain error specifies the maximum change from the initial (25°C) value to the value
Output Propagation Delay (tPD)
at TMIN or TMAX. The delay between the clock rising edge and the time when al bits are within valid logic levels.
Power Supply Rejection Ratio
The change in ful scale from the value with the supply at the
Out-of-Range Recovery Time
minimum limit to the value with the supply at its maximum limit. The time it takes for the ADC to reacquire the analog input after a transition from 10% above positive ful scale to 10%
Total Harmonic Distortion (THD)
1 above negative full scale, or from 10% below negative full scale The ratio of the rms input signal amplitude to the rms value of to 10% below positive full scale. the sum of the first six harmonic components. 1 AC specifications may be reported in dBc (degrades as signal levels are lowered) or in dBFS (always related back to converter full scale). Rev. C | Page 8 of 36 Document Outline Features Applications General Description Functional Block Diagram Product Highlights Revision History DC Specifications AC Specifications Digital Specifications Switching Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Terminology Pin Configurations and Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory of Operation Analog Input and Reference Overview Differential Input Configurations Single-Ended Input Configuration Clock Input Considerations Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Timing Voltage Reference Internal Reference Connection External Reference Operation Operational Mode Selection Evaluation Board TSSOP Evaluation Board LFCSP Evaluation Board Outline Dimensions Ordering Guide