Datasheet AD7763 (Analog Devices)

24-Bit, 625 kSPS, 109 dB Sigma-Delta ADC with On-Chip Buffers, Serial Interface Data Sheet AD7763 FEATURES FUNCTIONAL BLOCK DIAGRAM 120 dB dynamic range at 78 kHz output data rate V V IN– IN+ 109 dB dynamic range at 625 kHz output data rate 112 dB SNR at 78 kHz output data rate MULTIBIT AV DIFF
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107 dB SNR at 625 kHz output data rate MODULATOR AVDD2 625 kHz maximum fully filtered output word rate AVDD3 VREF+ Programmable oversampling rate (32× to 256×) BUF RECONSTRUCTION AVDD4 REFGND Flexible serial interface DECAPA Fully differential modulator input DECAPB AD7763 PROGRAMMABLE RBIAS On-chip differential amplifier for signal buffering DECIMATION AGND MCLK Low-pass finite impulse response (FIR) filter with default MCLKGND VDRIVE or user-programmable coefficients CONTROL LOGIC SYNC I/O DVDD RESET Overrange alert bit OFFSET AND GAIN FIR FILTER SH2:0 DGND REGISTERS ENGINE Digital offset and gain correction registers ADR2:0 CDIV Low power and power-down modes Synchronization of multiple devices via SYNC pin
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2 O O I FS SC SC SDL SD SC FSO SD I2S interface mode DRD
05476- Figure 1.
APPLICATIONS Data acquisition systems Vibration analysis Instrumentation GENERAL DESCRIPTION
The differential input is sampled at up to 40 MSPS by an analog modulator. The modulator output is processed by a series of The AD7763 high performance, 24-bit, Σ-Δ analog-to-digital low-pass filters, the final filter having default or user-programmable converter (ADC) combines wide input bandwidth and high coefficients. The sample rate, filter corner frequencies, and speed with the benefits of Σ-Δ conversion, as well as performance output word rate are set by a combination of the external clock of 107 dB SNR at 625 kSPS, making it ideal for high speed data frequency and the configuration registers of the AD7763. acquisition. A wide dynamic range, combined with significantly reduced antialiasing requirements, simplifies the design process. The reference voltage supplied to the AD7763 determines the An integrated buffer to drive the reference, a differential ampli- analog input range. With a 4 V reference, the analog input range fier for signal buffering and level shifting, an overrange flag, is ±3.2 V differential-biased around a common mode of 2 V. internal gain and offset registers, and a low-pass, digital FIR This common-mode biasing can be achieved using the on-chip filter make the AD7763 a compact, highly integrated data differential amplifiers, further reducing the external signal acquisition device requiring minimal peripheral component conditioning requirements. selection. In addition, the device offers programmable The AD7763 is available in an exposed paddle, 64-lead TQFP_EP decimation rates and a digital FIR filter, which can be user- and is specified over the industrial temperature range from programmed to ensure that its characteristics are tailored for the −40°C to +85°C. user’s application. The AD7763 is ideal for applications demanding high SNR without necessitating the design of complex, front-
Table 1. Related Devices
end signal processing.
Part No. Description
AD7760 24-bit, 2.5 MSPS, 100 dB Σ-Δ, parallel interface AD7762 24-bit, 625 kSPS, 109 dB Σ-Δ, parallel interface
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Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Terminology Typical Performance Characteristics Theory of Operation AD7763 Interface Reading Data Using the SPI Interface Synchronization Sharing the Serial Bus Writing to the AD7763 Reading Status and Other Registers Reading Data Using the I2S Interface Clocking the AD7763 Example 1 Example 2 Driving the AD7763 Using the AD7763 Bias Resistor Selection Decoupling and Layout Recommendations Supply Decoupling Additional Decoupling Reference Voltage Filtering Differential Amplifier Components Exposed Paddle Layout Considerations Programmable FIR Filter Downloading a User-Defined Filter Example Filter Download Registers Control Register 1—Address 0x001 Default Value 0x001A Control Register 2—Address 0x002 Default Value 0x009B Status Register (Read Only) Offset Register—Address 0x003 Non Bit-Mapped, Default Value 0x0000 Gain Register—Address 0x004 Non Bit-Mapped, Default Value 0xA000 Overrange Register—Address 0x005 Non Bit-Mapped, Default Value 0xCCCC Outline Dimensions Ordering Guide