Datasheet AD7193 (Analog Devices)

4-Channel, 4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA Data Sheet AD7193 FEATURES Pressure measurement Fast settling filter option Temperature measurement 4 differential/8 pseudo differential input channels Flow measurement RMS noise: 11 nV @ 4.7 Hz (gain = 128) Weigh scales 15.5 noise-free bits @ 2.4 kHz (gain = 128) Chromatography Up to 22 noise-free bits (gain = 1) Medical and scientific instrumentation Offset drift: ±5 nV/°C GENERAL DESCRIPTION Gain drift: ±1 ppm/°C
The AD7193 is a low noise, complete analog front end for high
Specified drift over time
precision measurement applications. It contains a low noise,
Automatic channel sequencer
24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC).
Programmable gain (1 to 128) Output data rate: 4.7 Hz to 4.8 kHz
The on-chip low noise gain stage means that signals of small
Internal or external clock
amplitude can interface directly to the ADC.
Simultaneous 50 Hz/60 Hz rejection
The device can be configured to have four differential inputs or
4 general-purpose digital outputs
eight pseudo differential inputs. The on-chip channel sequencer
Power supply
allows several channels to be enabled simultaneously, and the
AVDD: 3 V to 5.25 V
AD7193 sequential y converts on each enabled channel, simplifying
DVDD: 2.7 V to 5.25 V
communication with the part. The on-chip 4.92 MHz clock can
Current: 4.65 mA
be used as the clock source to the ADC or, alternatively, an external
Temperature range: −40°C to +105°C
clock or crystal can be used. The output data rate from the part
28-lead TSSOP and 32-lead LFCSP packages
can be varied from 4.7 Hz to 4.8 kHz.
Interface
The device has a very flexible digital filter, including a fast
3-wire serial
settling option. Variables such as output data rate and settling
SPI, QSPI™, MICROWIRE™, and DSP compatible
time are dependent on the option selected. The AD7193 also
Schmitt trigger on SCLK
includes a zero latency option.
APPLICATIONS
The part operates with a power supply from 3 V to 5.25 V. It
PLC/DCS analog input modules
consumes a current of 4.65 mA, and it is available in a 28-lead
Data acquisition
TSSOP package and a 32-lead LFCSP package.
Strain gage transducers FUNCTIONAL BLOCK DIAGRAM AV DV DD AGND DD DGND REFIN1(+) REFIN1(–) AD7193 AIN1 AIN2 AIN3 AIN4 SERIAL DOUT/RDY AIN5 INTERFACE MUX DIN Σ-Δ AIN6 PGA AND ADC CONTROL AIN7 SCLK LOGIC AIN8 CS AINCOM SYNC TEMP P3 SENSOR BPDSW P2 CLOCK CIRCUITRY AGND
001
MCLK1 MCLK2 P0/REFIN2(–) P1/REFIN2(+)
08367- Figure 1.
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Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS Circuit and Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS RMS NOISE AND RESOLUTION SINC4 CHOP DISABLED SINC3 CHOP DISABLED FAST SETTLING ON-CHIP REGISTERS COMMUNICATIONS REGISTER RS2, RS1, RS0 = 000 STATUS REGISTER RS2, RS1, RS0 = 000; Power-On/Reset = 0x80 MODE REGISTER RS2, RS1, RS0 = 001; Power-On/Reset = 0x080060 CONFIGURATION REGISTER RS2, RS1, RS0 = 010; Power-On/Reset = 0x000117 DATA REGISTER RS2, RS1, RS0 = 011; Power-On/Reset = 0x000000 ID REGISTER RS2, RS1, RS0 = 100; Power-On/Reset = 0xX2 GPOCON REGISTER RS2, RS1, RS0 = 101; Power-On/Reset = 0x00 OFFSET REGISTER RS2, RS1, RS0 = 110; Power-On/Reset = 0x800000) FULL-SCALE REGISTER RS2, RS1, RS0 = 111; Power-On/Reset = 0x5XXXX0 ADC CIRCUIT INFORMATION OVERVIEW Analog Inputs Multiplexer PGA Reference Detect Burnout Currents Sigma-Delta (Σ-Δ) ADC and Filter Serial Interface Clock Bridge Power-Down Switch Temperature Sensor Digital Outputs Calibration ANALOG INPUT CHANNEL PROGRAMMABLE GAIN ARRAY (PGA) REFERENCE REFERENCE DETECT BIPOLAR/UNIPOLAR CONFIGURATION DATA OUTPUT CODING BURNOUT CURRENTS CHANNEL SEQUENCER DIGITAL INTERFACE Single Conversion Mode Continuous Conversion Mode Continuous Read RESET SYSTEM SYNCHRONIZATION ENABLE PARITY CLOCK BRIDGE POWER-DOWN SWITCH TEMPERATURE SENSOR LOGIC OUTPUTS CALIBRATION DIGITAL FILTER SINC4 FILTER (CHOP DISABLED) Sinc4 Output Data Rate/Settling Time Sinc4 Zero Latency Sinc4 50 Hz/60 Hz Rejection SINC3 FILTER (CHOP DISABLED) Sinc3 Output Data Rate and Settling Time Sinc3 Zero Latency Sinc3 50 Hz/60 Hz Rejection CHOP ENABLED (SINC4 FILTER) Output Data Rate and Settling Time (Sinc4 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc4 Chop Enabled) CHOP ENABLED (SINC3 FILTER) Output Data Rate and Settling Time (Sinc3 Chop Enabled) 50 Hz/60 Hz Rejection (Sinc3 Chop Enabled) FAST SETTLING MODE (SINC4 FILTER) Output Data Rate and Settling Time, Sinc4 Filter 50 Hz/60 Hz Rejection, Sinc4 Filter FAST SETTLING MODE (SINC3 FILTER) Output Data Rate and Settling Time, Sinc3 Filter 50 Hz/60 Hz Rejection, Sinc3 Filter FAST SETTLING MODE (CHOP ENABLED) SUMMARY OF FILTER OPTIONS GROUNDING AND LAYOUT APPLICATIONS INFORMATION FLOWMETER OUTLINE DIMENSIONS ORDERING GUIDE