Datasheet AD9204 (Analog Devices)

10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter Data Sheet AD9204 FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V analog supply operation AVDD GND SDIO SCLK CSB 1.8 V to 3.3 V output supply SNR SPI ORA 61.3 dBFS at 9.7 MHz input R 61.0 dBFS at 200 MHz input FFE VIN+A PROGRAMMING DATA D9A S U O SFDR ADC T B VIN–A CM U D0A 75 dBc at 9.7 MHz input TP OU 73 dBc at 200 MHz input DCOA VREF Low power TION SENSE DRVDD 30 mW per channel at 20 MSPS AD9204 OP X VCM REF U 63 mW per channel at 80 MSPS SELECT M ORB RBIAS R Differential input with 700 MHz bandwidth FFE D9B On-chip voltage reference and sample-and-hold circuit VIN–B S U ADC O T B DNL = ±0.11 LSB VIN+B CM U D0B TP Serial port control options OU DCOB Scalable analog input: 1 V p-p to 2 V p-p differential Offset binary, gray code, or twos complement data format DIVIDE DUTY CYCLE MODE 1 TO 8 STABILIZER CONTROLS Optional clock duty cycle stabilizer
001
Integer 1-to-8 input clock divider CLK+ CLK– SYNC DCS PDWN DFS OEB
08122-
Built-in selectable digital test pattern generation
Figure 1.
Energy-saving power-down modes Data clock out with programmable clock and data PRODUCT HIGHLIGHTS alignment
1. The AD9204 operates from a single 1.8 V analog power
APPLICATIONS
supply and features a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.
Communications
2. The patented sample-and-hold circuit maintains excel ent
Diversity radio systems
performance for input frequencies up to 200 MHz and is
Multimode digital receivers
designed for low cost, low power, and ease of use.
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
3. A standard serial port interface supports various product
I/Q demodulation systems
features and functions, such as data output formatting,
Smart antenna systems
internal clock divider, power-down, DCO/DATA timing
Battery-powered instruments
and offset adjustments, and voltage reference modes.
Handheld scope meters
4. The AD9204 is packaged in a 64-lead RoHS compliant
Ultrasound
LFCSP that is pin compatible with the AD9268 16-bit
Radar/LIDAR
ADC, the AD9251 and AD9258 14-bit ADCs, and the
PET/SPECT imaging
AD9231 12-bit ADC, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS.
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Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9204-80 AD9204-65 AD9204-40 AD9204-20 Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Differential Input Configurations Single-Ended Input Configuration Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Digital Outputs Digital Output Enable Function (OEB) Timing Data Clock Output (DCO) Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Channel/Chip Synchronization Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Descriptions Sync Control (Register 0x100) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only Bit 1—Clock Divider Sync Enable Bit 0—Master Sync Enable USR2 (Register 0x101) Bit 7—Enable OEB Pin 47 Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide