Datasheet AD9629 (Analog Devices) - 2

AD9629* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS REFERENCE DESIGNS
View a parametric search of comparable parts. • CN0272
EVALUATION KITS REFERENCE MATERIALS
• AD9629 Evaluation Board
Technical Articles
• Improve The Design Of Your Passive Wideband ADC
DOCUMENTATION
Front-End Network
Application Notes
• MS-2210: Designing Power Supplies for High Speed ADC • AN-1142: Techniques for High Speed ADC PCB Layout • AN-586: LVDS Outputs for High Speed A/D Converters
DESIGN RESOURCES
• AN-742: Frequency Domain Response of Switched- • AD9629 Material Declaration Capacitor ADCs • PCN-PDN Information • AN-807: Multicarrier WCDMA Feasibility • Quality And Reliability • AN-808: Multicarrier CDMA2000 Feasibility • Symbols and Footprints • AN-812: MicroController-Based Serial Port Interface (SPI) Boot Circuit
DISCUSSIONS
• AN-827: A Resonant Approach to Interfacing Amplifiers to View all AD9629 EngineerZone Discussions. Switched-Capacitor ADCs • AN-878: High Speed ADC SPI Control Software
SAMPLE AND BUY
• AN-935: Designing an ADC Transformer-Coupled Front Visit the product page to see pricing options. End
Data Sheet TECHNICAL SUPPORT
• AD9629: 12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 Submit a technical question or find your regional support V Analog-to-Digital Converter Data Sheet number.
User Guides
• Evaluating the AD9266/AD9649/AD9629/AD9609 Analog-
DOCUMENT FEEDBACK
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TOOLS AND SIMULATIONS
• Visual Analog • AD9629 IBIS Models
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9629-80 AD9629-65 AD9629-40 AD9629-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS USR2 (Register 0x101) Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port Soft Reset OUTLINE DIMENSIONS ORDERING GUIDE