Datasheet AD9649 (Analog Devices) - 10

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Data Sheet AD9649 ABSOLUTE MAXIMUM RATINGS Table 6. THERMAL CHARACTERISTICS Parameter Rating
The exposed paddle is the only ground connection for the chip AVDD to AGND1 −0.3 V to +2.0 V and must be soldered to the analog ground plane of the user’s DRVDD to AGND1 −0.3 V to +3.9 V PCB. Soldering the exposed paddle to the user’s board also VIN+, VIN− to AGND1 −0.3 V to AVDD + 0.2 V increases the reliability of the solder joints and maximizes the CLK+, CLK− to AGND1 −0.3 V to AVDD + 0.2 V thermal capability of the package. VREF to AGND1 −0.3 V to AVDD + 0.2 V SENSE to AGND1 −0.3 V to AVDD + 0.2 V
Table 7. Thermal Resistance
VCM to AGND1 −0.3 V to AVDD + 0.2 V
Airflow
RBIAS to AGND1 −0.3 V to AVDD + 0.2 V
Package Velocity Type (m/sec) θ 1, 2 θ 1, 3 θ 1, 4
Ψ
1,2 Unit
CSB to AGND1 −0.3 V to DRVDD + 0.3 V
JA JC JB JT
32-Lead LFCSP 0 37.1 3.1 20.7 0.3 °C/W SCLK/DFS to AGND1 −0.3 V to DRVDD + 0.3 V 5 mm × 5 mm 1.0 32.4 0.5 °C/W SDIO/PDWN to AGND1 −0.3 V to DRVDD + 0.3 V 2.5 29.1 0.8 °C/W MODE/OR to AGND1 −0.3 V to DRVDD + 0.3 V D0 through D13 to AGND1 −0.3 V to DRVDD + 0.3 V 1 Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). DCO to AGND1 −0.3 V to DRVDD + 0.3 V 3 Per MIL-Std 883, Method 1012.1. Operating Temperature Range (Ambient) −40°C to +85°C 4 Per JEDEC JESD51-8 (still air). Maximum Junction Temperature Under Bias 150°C Typical θ Storage Temperature Range (Ambient) −65°C to +150°C JA is specified for a 4-layer PCB with a solid ground plane. As shown in Table 7, airflow improves heat dissipation, 1 AGND refers to the analog ground of the customer’s PCB. which reduces θJA. In addition, metal in direct contact with the Stresses at or above those listed under Absolute Maximum package leads from metal traces, through holes, ground, and Ratings may cause permanent damage to the product. This is a power planes, reduces the θJA. stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational
ESD CAUTION
section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 9 of 32 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9649-80 AD9649-65 AD9649-40 AD9649-20 EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations Single-Ended Input Configuration VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS Digital Output Enable Function (OEB) TIMING Data Clock Output (DCO) BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST BUILT-IN SELF-TEST (BIST) OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE OPEN LOCATIONS DEFAULT VALUES Logic Levels Transfer Register Map MEMORY MAP REGISTER TABLE MEMORY MAP REGISTER DESCRIPTIONS USR2 (Register 0x101) Bit 3—Enable GCLK Detect Bit 2—Run GCLK Bit 0—Disable SDIO Pull-Down APPLICATIONS INFORMATION DESIGN GUIDELINES Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations Encode Clock VCM RBIAS Reference Decoupling SPI Port Soft Reset OUTLINE DIMENSIONS ORDERING GUIDE