Datasheet HMCAD1520 (Analog Devices) - 7

HMCAD1520
v04.1015
HigH Speed Multi-Mode 8/12/14-Bit 1000/640/105 MSpS A/d Converter digital and Switching Specifications
AvDD = DvDD = ovDD = 1.8v, rsDs output data levels, unless otherwise noted.
Parameter Description Min Typ Max Unit
v High Level Input voltage. v ≥ 3.0v 2 v HI ovDD v High Level Input voltage. v = 1.7v – 3.0v 0.8 ·v v HI ovDD ovDD v Low Level Input voltage. v ≥ 3.0v 0 0.8 v LI ovDD v Low Level Input voltage. v = 1.7v – 3.0v 0 0.2 ·v v LI ovDD ovDD I High Level Input leakage Current +/-10 µA HI I Low Level Input leakage Current +/-10 µA LI C Input Capacitance 3 pF I
Data outputs
Compliance LvDs / rsDs 0 v Differential output voltage, LvDs 350 mv oUt v Differential output voltage, rsDs 150 mv oUt v output common mode voltage 1.2 v t CM output coding Default/optional offset Binary/ 2’s complement M s
Timing Characteristics
t Aperture delay, High speed modes 1.5 ns A,Hs s - t Aperture delay, Precision mode 1.4 ns A,PM r t Aperture jitter, all bits set to ‘1’ in jitter_ctrl<7:0>, High speed modes 120 fsrms j,Hs e t Aperture jitter, one bit set to ‘1’ in jitter_ctrl<7:0>, High speed modes 160 fsrms t j,Hs r t Aperture jitter, all bits set to ‘1’ in jitter_ctrl<7:0>, Precision modes 75 fsrms j,PM e t Aperture jitter, one bit set to ‘1’ in jitter_ctrl<7:0>, Precision modes 130 fsrms j,PM v t timing skew between ADC channels, High speed modes 2.5 psrms skew n start up time from Power Down Mode and Deep sleep Mode to o t 15 µs sU Active Mode in µs. see section “Clock Frequency” for details. t start up time from sleep Channel Mode to Active Mode 0.5 µs sLPCH t out of range recovery time 1 clock cycles ovr t Pipeline delay, Precision speed Mode 15 clock cycles LAtPM A / D C t Pipeline delay, Quad High speed Mode 32 clock cycles LAtHsMQ t Pipeline delay, Dual High speed Mode 64 clock cycles LAtHsMD t Pipeline delay, single High speed Mode 128 clock cycles LAtHsMs
LVDS Output Timing Characteristics
t LCLK to data delay time (excluding programmable phase shift) 50 ps data t Clock propagation delay. 6*t +2.2 7*t +3.5 7*t +5.0 ns ProP LvDs LvDs LvDs LvDs bit-clock duty-cycle 45 55 % LCLK cycle Frame clock cycle-to-cycle jitter 2.5 % LCLK cycle t Data rise- and fall time 20% to 80% 0.7 ns eDGe t Clock rise- and fall time 20% to 80% 0.7 ns CLKeDGe Informatio For price, delivery, and to place orders: Analog Devices, Inc., One Technology Way, P.O. Box 9106, Norwood, n furnished by Analog Devices is believed to be accurate and reliable. However, no For price, delivery, and to place orders: Analog Devices, Inc., responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other MA 02062-9106One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Phone: 781-329-4700 • Order online at www.analog.com
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