Datasheet AD7988-1, AD7988-5 (Analog Devices) - 5
| Fabricante | Analog Devices |
| Descripción | 16-Bit, 500ksps, Ultra Lower Power 16 bit SAR ADC |
| Páginas / Página | 23 / 5 — Data Sheet. AD7988-1/AD7988-5. TIMING SPECIFICATIONS. Table 4. Parameter. … |
| Revisión | G |
| Formato / tamaño de archivo | PDF / 591 Kb |
| Idioma del documento | Inglés |
Data Sheet. AD7988-1/AD7988-5. TIMING SPECIFICATIONS. Table 4. Parameter. Symbol. Min. Typ. Max. Unit
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Data Sheet AD7988-1/AD7988-5 TIMING SPECIFICATIONS
VDD = 2.37 V to 2.63 V, VIO = 3.3 V to 5.5 V, −40°C to +125°C unless otherwise stated. See Figure 2 and Figure 3 for load conditions.
Table 4. Parameter Symbol Min Typ Max Unit
AD7988-1 Throughput Rate 100 kHz Conversion Time: CNV Rising Edge to Data Available tCONV 9.5 μs Acquisition Time tACQ 500 ns Time Between Conversions tCYC 10 μs AD7988-5 Throughput Rate 500 kHz Conversion Time: CNV Rising Edge to Data Available tCONV B Grade 1.6 µs C Grade 1.2 µs Acquisition Time tACQ B Grade 400 ns C Grade 800 ns Time Between Conversions tCYC 2 μs CNV Pulse Width (CS Mode) tCNVH 500 ns SCK Period (CS Mode) tSCK VIO Above 4.5 V 10.5 ns VIO Above 3 V 12 ns VIO Above 2.7 V 13 ns VIO Above 2.3 V 15 ns SCK Period (Chain Mode) tSCK VIO Above 4.5 V 11.5 ns VIO Above 3 V 13 ns VIO Above 2.7 V 14 ns VIO Above 2.3 V 16 ns SCK Low Time tSCKL 4.5 ns SCK High Time tSCKH 4.5 ns SCK Falling Edge to Data Remains Valid tHSDO 3 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 4.5 V 9.5 ns VIO Above 3 V 11 ns VIO Above 2.7 V 12 ns VIO Above 2.3 V 14 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN VIO Above 3 V 10 ns VIO Above 2.3V 15 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 20 ns SDI Valid Setup Time from CNV Rising Edge tSSDICNV 5 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 2 ns SDI Valid Hold Time from CNV Rising Edge (Chain Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 2 ns SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 3 ns Rev. F | Page 5 of 23 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION Transfer Functions TYPICAL CONNECTION DIAGRAM ANALOG INPUTS DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE INPUT POWER SUPPLY DIGITAL INTERFACE MODE, 3-WIRE MODE 4-WIRE CHAIN MODE APPLICATIONS INFORMATION INTERFACING TO BLACKFIN® DSP LAYOUT EVALUATING THE PERFORMANCE OF THE AD7988-1/AD7988-5 OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7988-1/AD7988-5 TIMING SPECIFICATIONS
VDD = 2.37 V to 2.63 V, VIO = 3.3 V to 5.5 V, −40°C to +125°C unless otherwise stated. See Figure 2 and Figure 3 for load conditions.
Table 4. Parameter Symbol Min Typ Max Unit
AD7988-1 Throughput Rate 100 kHz Conversion Time: CNV Rising Edge to Data Available tCONV 9.5 μs Acquisition Time tACQ 500 ns Time Between Conversions tCYC 10 μs AD7988-5 Throughput Rate 500 kHz Conversion Time: CNV Rising Edge to Data Available tCONV B Grade 1.6 µs C Grade 1.2 µs Acquisition Time tACQ B Grade 400 ns C Grade 800 ns Time Between Conversions tCYC 2 μs CNV Pulse Width (CS Mode) tCNVH 500 ns SCK Period (CS Mode) tSCK VIO Above 4.5 V 10.5 ns VIO Above 3 V 12 ns VIO Above 2.7 V 13 ns VIO Above 2.3 V 15 ns SCK Period (Chain Mode) tSCK VIO Above 4.5 V 11.5 ns VIO Above 3 V 13 ns VIO Above 2.7 V 14 ns VIO Above 2.3 V 16 ns SCK Low Time tSCKL 4.5 ns SCK High Time tSCKH 4.5 ns SCK Falling Edge to Data Remains Valid tHSDO 3 ns SCK Falling Edge to Data Valid Delay tDSDO VIO Above 4.5 V 9.5 ns VIO Above 3 V 11 ns VIO Above 2.7 V 12 ns VIO Above 2.3 V 14 ns CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN VIO Above 3 V 10 ns VIO Above 2.3V 15 ns CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 20 ns SDI Valid Setup Time from CNV Rising Edge tSSDICNV 5 ns SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 2 ns SDI Valid Hold Time from CNV Rising Edge (Chain Mode) tHSDICNV 0 ns SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 2 ns SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 3 ns Rev. F | Page 5 of 23 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TYPICAL APPLICATION CIRCUIT TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION CIRCUIT INFORMATION CONVERTER OPERATION Transfer Functions TYPICAL CONNECTION DIAGRAM ANALOG INPUTS DRIVER AMPLIFIER CHOICE VOLTAGE REFERENCE INPUT POWER SUPPLY DIGITAL INTERFACE MODE, 3-WIRE MODE 4-WIRE CHAIN MODE APPLICATIONS INFORMATION INTERFACING TO BLACKFIN® DSP LAYOUT EVALUATING THE PERFORMANCE OF THE AD7988-1/AD7988-5 OUTLINE DIMENSIONS ORDERING GUIDE