Datasheet AD7176-2 (Analog Devices) - 6

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Data Sheet AD7176-2 Parameter Test Conditions/Comments Min Typ Max Unit
Long-Term Stability3 1000 hours 460 ppm Short Circuit ISC 25 mA EXTERNAL REFERENCE Reference Input Voltage Reference input = (REF+) – (REF−) 1 2.5 AVDD1 V Absolute Reference Input AVSS − 0.05 AVDD1 + 0.05 V Voltage Limits1 Average Reference Input ±72 µA/V Current Average Reference Input External clock ±1.2 nA/V/°C Current Drift Internal clock ±6 nA/V/°C Normal Mode Rejection1 See the Rejection parameter section of this table Common-Mode Rejection 83 dB GENERAL-PURPOSE I/O (GPIO 0, With respect to AVSS GPIO 1) Output High Voltage, V 1 OH ISOURCE = 200 µA AVSS + 4 V Output Low Voltage, V 1 OL ISINK = 800 µA AVSS + 0.4 V Input Mode Leakage Current1 −10 +10 µA Floating-State Output 5 pF Capacitance Input High Voltage, V 1 IH AVSS + 3 V Input Low Voltage, V 1 IL AVSS + 0.7 V CLOCK Internal Clock Frequency 16 MHz Accuracy −2.5 +2.5 % Duty Cycle 50:50 % Output Low Voltage, VOL 0.4 V Output High Voltage, VOH 0.8 × IOVDD V Crystal Frequency 14 16 16.384 MHz Start-Up Time 10 µs External Clock (CLKIO) 16 16.384 MHz Duty Cycle1 Typical duty cycle 50:50 (max:min) 30 50:50 70 % LOGIC INPUTS Input High Voltage, V 1 INH 2 V ≤ IOVDD ≤ 2.3 V 0.65 × IOVDD V 2.3 V ≤ IOVDD ≤ 5.5 V 0.7 × IOVDD V Input Low Voltage, V 1 INL 2 V ≤ IOVDD ≤ 2.3 V 0.35 × IOVDD V 2.3 V ≤ IOVDD ≤ 5.5 V 0.7 V Hysteresis1 IOVDD > 2.7 V 0.08 0.25 V IOVDD < 2.7 V 0.04 0.2 V Leakage Currents −10 +10 µA LOGIC OUTPUT (DOUT/RDY) Output High Voltage, V 1 OH IOVDD ≥ 4.5 V, ISOURCE = 1 mA 0.8 × IOVDD V 2.7 V ≤ IOVDD < 4.5 V, ISOURCE = 500 μA 0.8 × IOVDD V IOVDD < 2.7 V, ISOURCE = 200 μA 0.8 × IOVDD V Output Low Voltage, V 1 OL IOVDD ≥ 4.5 V, ISINK = 2 mA 0.4 V 2.7 V ≤ IOVDD < 4.5 V, ISINK = 1 mA 0.4 V IOVDD < 2.7 V, ISINK = 400 μA 0.4 V Leakage Current Floating state −10 +10 µA Output Capacitance Floating state 10 pF SYSTEM CALIBRATION1 Full-Scale Calibration Limit 1.05 × FS V Zero-Scale Calibration Limit −1.05 × FS V Input Span 0.8 × FS 2.1 × FS V Rev. D | Page 5 of 68 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES DIGITAL COMMUNICATION Accessing the ADC Register Map AD7176-2 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Offset Registers Gain Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION ANALOG INPUT Fully Differential Inputs Pseudo Differential Inputs DRIVER AMPLIFIERS AD8475 AD8656 ADA4940-1/ADA4940-2 AD7176-2 REFERENCE External Reference Internal Reference AD7176-2 CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION MODES DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS SERIAL INTERFACE RESET (DOUT_RESET) SYNCHRONIZATION (SYNC\/ERROR\) ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Pin DATA_STAT IOSTRENTGH GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL MAP REGISTER 0 CHANNEL MAP REGISTER 1 CHANNEL MAP REGISTER 2 CHANNEL MAP REGISTER 3 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 SETUP CONFIGURATION REGISTER 2 SETUP CONFIGURATION REGISTER 3 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 FILTER CONFIGURATION REGISTER 2 FILTER CONFIGURATION REGISTER 3 OFFSET REGISTER 0 OFFSET REGISTER 1 OFFSET REGISTER 2 OFFSET REGISTER 3 GAIN REGISTER 0 GAIN REGISTER 1 GAIN REGISTER 2 GAIN REGISTER 3 OUTLINE DIMENSIONS ORDERING GUIDE