Datasheet AD7176-2 (Analog Devices) - 5
| Fabricante | Analog Devices |
| Descripción | 24-Bit, 250 kSPS Sigma Delta ADC with 20 µs Settling |
| Páginas / Página | 69 / 5 — AD7176-2. Data Sheet. SPECIFICATIONS. Table 1. Parameter. Test … |
| Revisión | D |
| Formato / tamaño de archivo | PDF / 1.1 Mb |
| Idioma del documento | Inglés |
AD7176-2. Data Sheet. SPECIFICATIONS. Table 1. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit
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AD7176-2 Data Sheet SPECIFICATIONS
AVDD1 = 4.5 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS, internal master clock = 16 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
ADC SPEED AND PERFORMANCE Output Data Rate (ODR) 5 250,000 SPS No Missing Codes1 Excluding sinc3 filter ≥125 kSPS 24 Bits Resolution See Table 6 Noise See Table 6 Noise Free Resolution Sinc5 + sinc1 filter (default) 250 kSPS, REF+ = 5 V 17.3 Bits 2.5 kSPS, REF+ = 5 V 20.1 Bits 5 SPS, REF+ = 5 V 22.4 Bits ACCURACY Integral Nonlinearity (INL) 2.5 V reference ±2.5 ±7 ppm of FSR 5 V reference ±7 ppm of FSR Offset Error2 Internal short ±40 µV Offset Drift Internal short ±110 nV/°C Offset Drift vs. Time3 ±450 nV/1000 hours Gain Error2 25°C ±10 ±50 ppm/FSR Gain Drift vs. Temperature1 ±0.5 ±1 ppm/FSR/°C Gain Drift vs. Time3 ±3 ppm/FSR/ 1000 hours REJECTION Power Supply Rejection AVDD1, AVDD2 VIN = 1 V 90 dB Common-Mode Rejection VIN = 0.1 V At DC 95 dB At 50 Hz and 60 Hz1 20 SPS ODR (post filter) 130 dB (50 Hz ± 1 Hz and 60 Hz ± 1 Hz) Normal Mode Rejection1 50 Hz ± 1 Hz and 60 Hz ± 1 Hz Internal clock, 20 SPS ODR (post filter) 71 90 dB External clock, 20 SPS ODR (post filter) 85 90 dB ANALOG INPUTS Differential Input Voltage Range ±VREF V Absolute AIN Voltage Limits1 AVSS − 0.050 AVDD1 + 0.05 V Analog Input Current Input Current ±48 µA/V Input Current Drift External clock ±0.75 nA/V/°C Internal clock (±2.5 % clock) ±4 nA/V/°C Crosstalk 1 kHz input −120 dB INTERNAL REFERENCE 100 nF external capacitor on REFOUT to AVSS Output Voltage REFOUT with respect to AVSS 2.5 V Initial Accuracy1 TA = 25°C4 − 0.16% + 0.16% V Temperature Coefficient 0°C to +105°C ±2 ±5 ppm/°C −40°C to +105°C ±3 ±10 ppm/°C Reference Load Current, ILOAD IL −10 +10 mA Power Supply Rejection (Line AVDD1 and AVDD2 93 dB Regulation) Load Regulation ∆VOUT/∆IL 32 ppm/mA Voltage Noise eN, 0.1 Hz to 10 Hz 4.5 µV rms Voltage Noise Density eN, 1 kHz 215 nV/√Hz Turn-On Settling Time 100 nF capacitor 60 µs Rev. D | Page 4 of 68 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES DIGITAL COMMUNICATION Accessing the ADC Register Map AD7176-2 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Offset Registers Gain Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION ANALOG INPUT Fully Differential Inputs Pseudo Differential Inputs DRIVER AMPLIFIERS AD8475 AD8656 ADA4940-1/ADA4940-2 AD7176-2 REFERENCE External Reference Internal Reference AD7176-2 CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION MODES DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS SERIAL INTERFACE RESET (DOUT_RESET) SYNCHRONIZATION (SYNC\/ERROR\) ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Pin DATA_STAT IOSTRENTGH GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL MAP REGISTER 0 CHANNEL MAP REGISTER 1 CHANNEL MAP REGISTER 2 CHANNEL MAP REGISTER 3 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 SETUP CONFIGURATION REGISTER 2 SETUP CONFIGURATION REGISTER 3 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 FILTER CONFIGURATION REGISTER 2 FILTER CONFIGURATION REGISTER 3 OFFSET REGISTER 0 OFFSET REGISTER 1 OFFSET REGISTER 2 OFFSET REGISTER 3 GAIN REGISTER 0 GAIN REGISTER 1 GAIN REGISTER 2 GAIN REGISTER 3 OUTLINE DIMENSIONS ORDERING GUIDE
AD7176-2 Data Sheet SPECIFICATIONS
AVDD1 = 4.5 V to 5.5 V, AVDD2 = 2 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = DGND = 0 V, REF+ = 2.5 V, REF− = AVSS, internal master clock = 16 MHz, TA = TMIN to TMAX, unless otherwise noted.
Table 1. Parameter Test Conditions/Comments Min Typ Max Unit
ADC SPEED AND PERFORMANCE Output Data Rate (ODR) 5 250,000 SPS No Missing Codes1 Excluding sinc3 filter ≥125 kSPS 24 Bits Resolution See Table 6 Noise See Table 6 Noise Free Resolution Sinc5 + sinc1 filter (default) 250 kSPS, REF+ = 5 V 17.3 Bits 2.5 kSPS, REF+ = 5 V 20.1 Bits 5 SPS, REF+ = 5 V 22.4 Bits ACCURACY Integral Nonlinearity (INL) 2.5 V reference ±2.5 ±7 ppm of FSR 5 V reference ±7 ppm of FSR Offset Error2 Internal short ±40 µV Offset Drift Internal short ±110 nV/°C Offset Drift vs. Time3 ±450 nV/1000 hours Gain Error2 25°C ±10 ±50 ppm/FSR Gain Drift vs. Temperature1 ±0.5 ±1 ppm/FSR/°C Gain Drift vs. Time3 ±3 ppm/FSR/ 1000 hours REJECTION Power Supply Rejection AVDD1, AVDD2 VIN = 1 V 90 dB Common-Mode Rejection VIN = 0.1 V At DC 95 dB At 50 Hz and 60 Hz1 20 SPS ODR (post filter) 130 dB (50 Hz ± 1 Hz and 60 Hz ± 1 Hz) Normal Mode Rejection1 50 Hz ± 1 Hz and 60 Hz ± 1 Hz Internal clock, 20 SPS ODR (post filter) 71 90 dB External clock, 20 SPS ODR (post filter) 85 90 dB ANALOG INPUTS Differential Input Voltage Range ±VREF V Absolute AIN Voltage Limits1 AVSS − 0.050 AVDD1 + 0.05 V Analog Input Current Input Current ±48 µA/V Input Current Drift External clock ±0.75 nA/V/°C Internal clock (±2.5 % clock) ±4 nA/V/°C Crosstalk 1 kHz input −120 dB INTERNAL REFERENCE 100 nF external capacitor on REFOUT to AVSS Output Voltage REFOUT with respect to AVSS 2.5 V Initial Accuracy1 TA = 25°C4 − 0.16% + 0.16% V Temperature Coefficient 0°C to +105°C ±2 ±5 ppm/°C −40°C to +105°C ±3 ±10 ppm/°C Reference Load Current, ILOAD IL −10 +10 mA Power Supply Rejection (Line AVDD1 and AVDD2 93 dB Regulation) Load Regulation ∆VOUT/∆IL 32 ppm/mA Voltage Noise eN, 0.1 Hz to 10 Hz 4.5 µV rms Voltage Noise Density eN, 1 kHz 215 nV/√Hz Turn-On Settling Time 100 nF capacitor 60 µs Rev. D | Page 4 of 68 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION GETTING STARTED POWER SUPPLIES DIGITAL COMMUNICATION Accessing the ADC Register Map AD7176-2 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Offset Registers Gain Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register Understanding Configuration Flexibility CIRCUIT DESCRIPTION ANALOG INPUT Fully Differential Inputs Pseudo Differential Inputs DRIVER AMPLIFIERS AD8475 AD8656 ADA4940-1/ADA4940-2 AD7176-2 REFERENCE External Reference Internal Reference AD7176-2 CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTERS SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION MODES DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE I/O EXTERNAL MULTIPLEXER CONTROL DELAY 16-BIT/24-BIT CONVERSIONS SERIAL INTERFACE RESET (DOUT_RESET) SYNCHRONIZATION (SYNC\/ERROR\) ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR Pin DATA_STAT IOSTRENTGH GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL MAP REGISTER 0 CHANNEL MAP REGISTER 1 CHANNEL MAP REGISTER 2 CHANNEL MAP REGISTER 3 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 SETUP CONFIGURATION REGISTER 2 SETUP CONFIGURATION REGISTER 3 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 FILTER CONFIGURATION REGISTER 2 FILTER CONFIGURATION REGISTER 3 OFFSET REGISTER 0 OFFSET REGISTER 1 OFFSET REGISTER 2 OFFSET REGISTER 3 GAIN REGISTER 0 GAIN REGISTER 1 GAIN REGISTER 2 GAIN REGISTER 3 OUTLINE DIMENSIONS ORDERING GUIDE