Datasheet AD9681 (Analog Devices) - 3
| Fabricante | Analog Devices |
| Descripción | Octal, 14-Bit, 125 MSPS, Serial LVDS, 1.8 V Analog-to-Digital Converter |
| Páginas / Página | 41 / 3 — AD9681. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 10/15—Rev. B to … |
| Revisión | C |
| Formato / tamaño de archivo | PDF / 1.6 Mb |
| Idioma del documento | Inglés |
AD9681. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 10/15—Rev. B to Rev. C. 12/13—Rev. 0 to Rev. A
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AD9681 Data Sheet TABLE OF CONTENTS
Features .. 1 Power Dissipation and Power-Down Mode ... 24 Applications ... 1 Digital Outputs and Timing ... 25 General Description ... 1 Output Test Modes ... 28 Simplified Functional Block Diagram ... 1 Serial Port Interface (SPI) .. 29 Product Highlights ... 1 Configuration Using the SPI ... 29 Revision History ... 2 Hardware Interface ... 30 Functional Block Diagram .. 3 Configuration Without the SPI .. 30 Specifications ... 4 SPI Accessible Features .. 30 DC Specifications ... 4 Memory Map .. 31 AC Specifications .. 5 Reading the Memory Map Register Table ... 31 Digital Specifications ... 6 Memory Map .. 32 Switching Specifications .. 7 Memory Map Register Descriptions .. 35 Timing Specifications .. 8 Applications Information .. 38 Absolute Maximum Ratings .. 12 Design Guidelines .. 38 Thermal Characteristics .. 12 Power and Ground Recommendations ... 38 ESD Caution .. 12 Board Layout Considerations ... 38 Pin Configuration and Function Descriptions ... 13 Clock Stability Considerations ... 39 Typical Performance Characteristics ... 16 VCM ... 39 Equivalent Circuits ... 19 Reference Decoupling .. 39 Theory of Operation .. 20 SPI Port .. 39 Analog Input Considerations .. 20 Outline Dimensions ... 40 Voltage Reference ... 21 Ordering Guide .. 40 Clock Input Considerations .. 22
REVISION HISTORY 10/15—Rev. B to Rev. C 12/13—Rev. 0 to Rev. A
Added Endnote 4, Table 4; Renumbered Sequentially .. 7 Changes to Ordering Guide .. 39 Changes to Clock Input Options Section .. 23 Changes to Digital Outputs and Timing Section ... 27
11/13—Revision 0: Initial Version 2/15—Rev. A to Rev. B
Changes to SYNC Timing Requirements Parameter, Table 5 .. 8 Changes to Figure 7 .. 10 Changes to Figure 8 .. 11 Changes to Table 8 .. 13 Changed AD9515-x to AD9515 ... 23 Changes to Digital Outputs and Timing Section and Table 11 ... 27 Rev. C | Page 2 of 40 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/OLM Pin SCLK/DTP Pin CSB1 and CSB2 Pins RBIAS1 and RBIAS2 Pins OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel Specific Registers MEMORY MAP MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Enhancement Control (Register 0x0C) Output Mode (Register 0x14) Output Adjust (Register 0x15) Output Phase (Register 0x16) Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) User I/O Control 3 (Register 0x102) APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS BOARD LAYOUT CONSIDERATIONS Sources of Coupling Crosstalk Between Inputs Coupling of Digital Output Switching Noise to Analog Inputs and Clock CLOCK STABILITY CONSIDERATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE
AD9681 Data Sheet TABLE OF CONTENTS
Features .. 1 Power Dissipation and Power-Down Mode ... 24 Applications ... 1 Digital Outputs and Timing ... 25 General Description ... 1 Output Test Modes ... 28 Simplified Functional Block Diagram ... 1 Serial Port Interface (SPI) .. 29 Product Highlights ... 1 Configuration Using the SPI ... 29 Revision History ... 2 Hardware Interface ... 30 Functional Block Diagram .. 3 Configuration Without the SPI .. 30 Specifications ... 4 SPI Accessible Features .. 30 DC Specifications ... 4 Memory Map .. 31 AC Specifications .. 5 Reading the Memory Map Register Table ... 31 Digital Specifications ... 6 Memory Map .. 32 Switching Specifications .. 7 Memory Map Register Descriptions .. 35 Timing Specifications .. 8 Applications Information .. 38 Absolute Maximum Ratings .. 12 Design Guidelines .. 38 Thermal Characteristics .. 12 Power and Ground Recommendations ... 38 ESD Caution .. 12 Board Layout Considerations ... 38 Pin Configuration and Function Descriptions ... 13 Clock Stability Considerations ... 39 Typical Performance Characteristics ... 16 VCM ... 39 Equivalent Circuits ... 19 Reference Decoupling .. 39 Theory of Operation .. 20 SPI Port .. 39 Analog Input Considerations .. 20 Outline Dimensions ... 40 Voltage Reference ... 21 Ordering Guide .. 40 Clock Input Considerations .. 22
REVISION HISTORY 10/15—Rev. B to Rev. C 12/13—Rev. 0 to Rev. A
Added Endnote 4, Table 4; Renumbered Sequentially .. 7 Changes to Ordering Guide .. 39 Changes to Clock Input Options Section .. 23 Changes to Digital Outputs and Timing Section ... 27
11/13—Revision 0: Initial Version 2/15—Rev. A to Rev. B
Changes to SYNC Timing Requirements Parameter, Table 5 .. 8 Changes to Figure 7 .. 10 Changes to Figure 8 .. 11 Changes to Table 8 .. 13 Changed AD9515-x to AD9515 ... 23 Changes to Digital Outputs and Timing Section and Table 11 ... 27 Rev. C | Page 2 of 40 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT CONSIDERATIONS Input Common Mode Differential Input Configurations VOLTAGE REFERENCE Internal Reference Connection External Reference Operation CLOCK INPUT CONSIDERATIONS Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations POWER DISSIPATION AND POWER-DOWN MODE DIGITAL OUTPUTS AND TIMING SDIO/OLM Pin SCLK/DTP Pin CSB1 and CSB2 Pins RBIAS1 and RBIAS2 Pins OUTPUT TEST MODES SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open Locations Default Values Logic Levels Channel Specific Registers MEMORY MAP MEMORY MAP REGISTER DESCRIPTIONS Device Index (Register 0x05) Transfer (Register 0xFF) Power Modes (Register 0x08) Enhancement Control (Register 0x0C) Output Mode (Register 0x14) Output Adjust (Register 0x15) Output Phase (Register 0x16) Serial Output Data Control (Register 0x21) Resolution/Sample Rate Override (Register 0x100) User I/O Control 2 (Register 0x101) User I/O Control 3 (Register 0x102) APPLICATIONS INFORMATION DESIGN GUIDELINES POWER AND GROUND RECOMMENDATIONS BOARD LAYOUT CONSIDERATIONS Sources of Coupling Crosstalk Between Inputs Coupling of Digital Output Switching Noise to Analog Inputs and Clock CLOCK STABILITY CONSIDERATIONS VCM REFERENCE DECOUPLING SPI PORT OUTLINE DIMENSIONS ORDERING GUIDE