Datasheet AD9691 (Analog Devices)

14-Bit, 1.25 GSPS JESD204B, Dual Analog-to-Digital Converter Data Sheet AD9691 FEATURES FUNCTIONAL BLOCK DIAGRAM JESD204B (Subclass 1) coded serial digital outputs AVDD1 AVDD2 AVDD3 AVDD_SR DVDD DRVDD SPIVDD (1.25V) (2.50V) (3.3V) (1.25V) (1.25V) (1.25V) (1.8V TO 3.3V) 1.9 W total power per channel (default settings) BUFFER SFDR = 77 dBFS at 340 MHz VIN+A ADC 14 CORE DIGITAL SNR = 63.4 dBFS at 340 MHz (A VIN–A LIZER SERDOUT0± IN = −1.0 dBFS) DOWN- IA TS SERDOUT1± CONVERTER U 8 Noise density = −152.6 dBFS/Hz FD_A SERDOUT2± T SER TP SERDOUT3± TECT SIGNAL MONITOR SD204B SERDOUT4± 1.25 V, 2.50 V, and 3.3 V dc supply operation FAS OU SERDOUT5± DE JE FD_B DIGITAL Tx SERDOUT6± No missing codes DOWN- SPEED SERDOUT7± 14 H VIN+B CONVERTER ADC IG 1.58 V p-p differential full scale input voltage H VIN–B CORE CONTROL Flexible termination impedance BUFFER REGISTERS FAST DETECT 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential V_1P0 AD9691 SIGNAL 1.5 GHz usable analog input full power bandwidth MONITOR JESD204B SYNCINB± CLOCK GENERATION SUBCLASS 1 95 dB channel isolation/crosstalk CONTROL SYSREF± CLK+ Amplitude detection bits for efficient AGC implementation CLK– ÷2 SPI CONTROL PDWN/ ÷4 STBY 2 integrated wideband digital processors per channel ÷8
001
12-bit NCO, up to 4 cascaded half-band filters AGND DRGND DGND SDIO SCLK CSB
13092-
Integer clock divide by 1, 2, 4, or 8
Figure 1.
Flexible JESD204B lane configurations Timestamp feature Small signal dither APPLICATIONS Communications (wideband receivers and digital predistortion) Instrumentation (spectrum analyzers, network analyzers,
this threshold indicator has low latency, the user can quickly
integrated RF test solutions)
turn down the system gain to avoid an overrange condition at
DOCSIS 3.x CMTS upstream receive paths
the ADC input.
High speed data acquisition systems
Users can configure the Subclass 1 JESD204B-based high speed
GENERAL DESCRIPTION
serialized output in a variety of one-, two-, four- or eight-lane configurations, depending on the DDC configuration and the The AD9691 is a dual, 14-bit, 1.25 GSPS analog-to-digital converter acceptable lane rate of the receiving logic device. Multiple device (ADC). The device has an on-chip buffer and sample-and-hold synchronization is supported through the SYSREF± input pins. circuit designed for low power, small size, and ease of use. The device is designed for sampling wide bandwidth analog signals The AD9691 is available in a Pb-free, 88-lead LFCSP and is of up to 1.5 GHz. specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each
PRODUCT HIGHLIGHTS
ADC features wide bandwidth inputs supporting a variety of 1. Low power consumption analog core, 14-bit, 1.25 GSPS user-selectable input ranges. An integrated voltage reference dual ADC with 1.9 W per channel. eases design considerations. 2. Wide ful power bandwidth supports intermediate Each ADC data output is internal y connected to two digital frequency (IF) sampling of signals up to 1.5 GHz. downconverters (DDCs). Each DDC consists of four cascaded 3. Buffered inputs with programmable input termination signal processing stages: a 12-bit frequency translator (NCO) eases filter design and implementation. and four half-band decimation filters. 4. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. In addition to the DDC blocks, the AD9691 has a programmable 5. Programmable fast overrange detection. threshold detector that al ows monitoring of the incoming 6. 12 mm × 12 mm, 88-lead LFCSP. signal power using the fast detect output bits of the ADC. Because
Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider ½ Period Delay Adjust Input Clock Divider Clock Fine Delay Adjust Clock Jitter Considerations POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR SPORT Over JESD204B DIGITAL DOWNCONVERTERS (DDCS) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO PLUS MIXER LOSS AND SFDR NUMERICALLY CONTROLLED OSCILLATOR Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR FILTERS GENERAL DESCRIPTION HALF-BAND FILTERS HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION BLOCK DDC EXAMPLE CONFIGURATIONS DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8B/10B Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop (PLL) CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode Example 2: ADC with DDC Option (Two ADCs Plus Two DDCs ) MULTICHIP SYNCHRONIZATION SYSREF± SETUP/HOLD WINDOW MONITOR TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Unassigned and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 78) AND AGND (PIN 77 AND PIN 81) OUTLINE DIMENSIONS ORDERING GUIDE