Datasheet AD9695 (Analog Devices) - 10

Data Sheet AD9695 Analog Input Full Analog Input Full Scale = Analog Input Full Scale = Scale = 1.36 V p-p 1.7 V p-p 2.04 V p-p Parameter1 Min Typ Max Min Typ Max Min Typ Ma Unit x
ANALOG INPUT BANDWIDTH, FULL 2 2 2 GHz POWER5 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Noise density is measured at a low analog input frequcency (10 MHz). 3 Crosstalk is measured at 10 MHz with a −1.0 dBFS analog input on one channel, and no input on the adjacent channel. 4 The overrange condition is specified with 3 dB of the full-scale input range. 5 Full power bandwidth is the bandwidth of operation to achieve proper ADC performance.
DIGITAL SPECIFICATIONS
AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD = 1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, and sample rate = 625 MSPS (AD9695-625 speed grade), sample rate = 1300 MSPS (AD9695-1300 speed grade), DCS on (AD9695-1300 speedgrade), DCS off (AD9695-625 speed grade), unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 35°C (TA = 25°C for the AD9695-625 speed grade) and TJ = 40°C (TA = 25°C for the AD9695-1300 speed grade).
Table 4. Parameter Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−) Logic Compliance LVDS/LVPECL Differential Input Voltage 400 800 1600 mV p-p Input Common-Mode Voltage 0.65 V Input Resistance (Differential) 32 kΩ Input Capacitance (Differential) 0.9 pF SYSREF INPUTS (SYSREF+, SYSREF−) Logic Compliance LVDS/LVPECL Differential Input Voltage 400 800 1800 mV p-p Input Common-Mode Voltage 0.65 2 V Input Resistance (Differential) 18 kΩ Input Capacitance (Differential) 1 pF LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY, FD_A/GPIO_A0, FD_B/GPIO_B0) Logic Compliance CMOS Logic 1 Voltage 0.75 × SPIVDD V Logic 0 Voltage 0 0.35 × SPIVDD V Input Resistance 30 kΩ LOGIC OUTPUT (SDIO, FD_A, FD_B) Logic Compliance CMOS Logic 1 Voltage (IOH = 4 mA) SPIVDD − 0.45 V Logic 0 Voltage (IOL = 4 mA) 0 0.45 V SYNCIN INPUTS (SYNCINB−, SYNCINB+) Logic Compliance LVDS/LVPECL/CMOS Differential Input Voltage 400 800 1800 mV p-p Input Common-Mode Voltage 0.65 2 V Input Resistance (Differential) 18 kΩ Input Capacitance (Single-Ended per Pin) 1 pF DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 3) Logic Compliance SST Differential Output Voltage 360 520 770 mV p-p Differential Termination Impedance 80 100 1200 Ω Rev. 0 | Page 9 of 135 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS—1300 MSPS AC SPECIFICATIONS—625 MSPS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 1300 MSPS 625 MSPS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Absolute Maximum Input Swing Dither VOLTAGE REFERENCE DC OFFSET CALIBRATION CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay and Superfine Delay Adjust Clock Coupling Considerations Clock Jitter Considerations POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) ADC APPLICATION MODES AND JESD204B Tx CONVERTER MAPPING PROGRAMMABLE FINITE IMPULSE RESPONSE (FIR) FILTERS SUPPORTED MODES PROGRAMMING INSTRUCTIONS DIGITAL DOWNCONVERTER (DDC) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION DDC FREQUENCY TRANSLATION DDC Frequency Translation General Description Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO Description DDC NCO Programmable Modulus Mode DDC NCO Coherent Mode NCO FTW/POW/MAW/MAB Description NCO FTW/POW/MAW/MAB Programmable Modulus Mode NCO FTW/POW/MAW/MAB Coherent Mode NCO Channel Selection GPIO Level Control Mode GPIO Edge Control Mode Register Map Mode Setting Up the Multichannel NCO Feature NCO Synchronization NCO Multichip Synchronization NCO Multichip Synchronization at Startup NCO Multichip Synchronization During Normal Operation DDC Mixer Description DDC NCO + Mixer Loss and SFDR DDC DECIMATION FILTERS HB4 Filter Description HB3 Filter Description HB2 Filter Description HB1 Filter Description TB2 Filter Description TB1 Filter Description FB2 Filter Description DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC MIXED DECIMATION SETTINGS DDC EXAMPLE CONFIGURATIONS SIGNAL MONITOR SPORT OVER JESD204B DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls Deemphasis Phase-Locked Loop (PLL) SETTING UP THEAD9695 DIGITAL INTERFACE Example Setup 1—Full Bandwidth Mode Example Setup 2—ADC with DDC Option (Two ADCs Plus Two DDCs) DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency registers MULTICHIP SYNCHRONIZATION NORMAL MODE TIMESTAMP MODE SYSREF± INPUT SYREF± Control Features SYSREF± SETUP/HOLD WINDOW MONITOR LATENCY END TO END TOTAL LATENCY EXAMPLE LATENCY CALCULATIONS LMFC REFERENCED LATENCY TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel Specific Registers SPI Soft Reset MEMORY MAP REGISTERS APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS LAYOUT GUIDELINES AVDD1_SR (PIN 57) AND AGND_SR (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE