Datasheet AD7719 (Analog Devices) - 9

AD7719 DIGITAL INTERFACE
of the output register to indicate when not to read from the device As previously outlined, the AD7719’s programmable functions are to ensure that a data read is not attempted while the register is controlled using a set of on-chip registers. Data is written to these being updated. CS is used to select the device. It can be used to registers via the part’s serial interface; read access to the on-chip decode the AD7719 in systems where a number of parts are registers is also provided by this interface. All communications to connected to the serial bus. the part must start with a write operation to the Communications Figures 2 and 3 show timing diagrams for interfacing to the register. After power-on or RESET, the device expects a write to AD7719 with CS used to decode the part. Figure 3 is for a read its Communications register. The data written to this register operation from the AD7719’s output shift register while Figure 2 determines whether the next operation to the part is a read or a shows a write operation to the input shift register. It is possible write operation and also determines to which register this read to read the same data twice from the output register even though or write operation occurs. Therefore, write access to any of the the RDY line returns high after the first read operation. Care must other registers on the part starts with a write operation to the be taken, however, to ensure that the read operations have been Communications register followed by a write to the selected completed before the next output update is about to take place. register. A read operation from any other register on the part (including the output data register) starts with a write operation The AD7719 serial interface can operate in 3-wire mode by tying to the Communications register followed by a read operation the CS input low. In this case, the SCLK, DIN, and DOUT lines from the selected register. are used to communicate with the AD7719, and the status of RDY bits (RDY0 and RDY1) can be obtained by interrogating The AD7719’s serial interface consists of five signals: CS, SCLK, the STATUS register. This scheme is suitable for interfacing to DIN, DOUT, and RDY. The DIN line is used for transferring microcontrollers. If CS is required as a decoding signal, it can data into the on-chip registers while the DOUT line is used for be generated from a port bit. For microcontroller interfaces, it is accessing data from the on-chip registers. SCLK is the serial recommended that the SCLK idles high between data transfers. clock input for the device, and all data transfers (either on DIN or DOUT) take place with respect to this SCLK signal. The The AD7719 can also be operated with CS used as a frame syn- RDY line is used as a status signal to indicate when data is ready chronization signal. This scheme is suitable for DSP interfaces. to be read from the AD7719’s data register. RDY goes low when a In this case, the first bit (MSB) is effectively clocked out by CS new data-word is available in the output register of either the since CS would normally occur after the falling edge of SCLK main or aux ADCs. It is reset high when a read operation from in DSPs. The SCLK can continue to run between data transfers the data register is complete. It also goes high prior to the updating provided the timing numbers are obeyed.
CS t11 t t 14 16 SCLK t15 t12 t13 DIN MSB LSB
Figure 2. Write Cycle Timing Diagram
RDY t3 t10 CS t t8 4 t6 SCLK t t 7 t6 5 t t 5A 9 DOUT MSB LSB
Figure 3. Read Cycle Timing Diagram –8– REV. A Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE TIMING CHARACTERISTICS DIGITAL INTERFACE PIN CONFIGURATION PIN FUNCTION DESCRIPTIONS Typical Performance Characteristics DUAL-CHANNEL ADC CIRCUIT INFORMATION Overview Main Channel Auxiliary Channel Both Channels MAIN AND AUXILIARY ADC NOISE PERFORMANCE ON-CHIP REGISTERS Communications Register (A3, A2, A1, A0 = 0, 0, 2, 0) Status Register (A3, A2, A1, A0 = 0, 0, 0, 0; Power-On Reset = 0x00) Mode Register (A3, A2, A1, A0 = 0, 0, 0, 1; Power-On Reset = 0x00) Operating Characteristics when Addressing the Mode and Control Registers Main ADC Control Register (AD0CON): (A3, A2, A1, A0 = 0, 0, 1, 0; Power-On Reset = 0x07) Aux ADC Control Registers (AD1CON): (A3, A2, A1, A0 = 0, 0, 1, 1; Power-On Reset = 0x00) Filter Register (A3, A2, A1, A0 = 0, 1, 0, 0; Power-On Reset = 0x45) I/O and Current Source Control Register (IOCON): (A3, A2, A1, A0 = 0, 1, 1, 1; Power-On Reset = 0x0000) Main ADC Data Result Registers (DATA0): (A3, A2, A1, A0 = 0, 1, 0, 1; Power-On Reset = 0x00 0000) Aux ADC Data Result Registers (DATA1): (A3, A2, A1, A0 = 0, 1, 1, 0; Power-On Reset = 0x0000) Main ADC Offset Calibration Coefficient Registers (OF0): (A3, A2, A1, A0 = 1, 0, 0, 0; Power-On Reset = 0x80 0000) Aux ADC Offset Calibration Coefficient Registers (OF1): (A3, A2, A1, A0 = 1, 0, 0, 1; Power-On Reset = 0x8000) Main ADC Gain Calibration Coefficient Registers (GNO): (A3, A2, A1, A0 = 1, 0, 1, 0; Power-On Reset = 0x5X XXX5) Aux ADC Gain Calibration Coefficient Registers (GN1): (A3, A2, A1, A0 = 1, 0, 1, 1; Power-On Reset = 0x59XX) ID Register (ID): (A3, A2, A1, A0 = 1, 1, 1, 1; Power-On Reset = 0x0X) User Nonprogrammable Test Registers CONFIGURING THE AD7719 MICROCOMPUTER/MICROPROCESSOR INTERFACING AD7719-to-68HC11 Interface AD7719-to-8xC51 Interface AD7719-to-ADSP-2103/ADSP-2105 Interface CIRCUIT DESCRIPTION Analog Input Channels Programmable Gain Amplifier Bipolar/Unipolar Configuration Data Output Coding Burnout Currents Excitation Currents Crystal Oscillator Reference Input Reference Detect Reset Input Power-Down Mode Idle Mode ADC Disable Mode Calibration Grounding and Layout APPLICATIONS Pressure Measurement Temperature Measurement 3-Wire RTD Configurations Smart Transmitters OUTLINE DIMENSIONS Revision History