Datasheet LTC1772 (Analog Devices) - 10
| Fabricante | Analog Devices |
| Descripción | Constant Frequency Current Mode Step-Down DC/DC Controller in SOT-23 |
| Páginas / Página | 12 / 10 — APPLICATIONS INFORMATION. PC Board Layout Checklist. Foldback Current … |
| Formato / tamaño de archivo | PDF / 172 Kb |
| Idioma del documento | Inglés |
APPLICATIONS INFORMATION. PC Board Layout Checklist. Foldback Current Limiting. Figure 5. Foldback Current Limiting
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LTC1772
U U W U APPLICATIONS INFORMATION
0.4V, the loss increases from 0.5% to 8% as the load will be reduced to approximately 50% of the maximum current increases from 0.5A to 2A. output current. 5. Transition losses apply to the external MOSFET and
PC Board Layout Checklist
increase at higher operating frequencies and input voltages. Transition losses can be estimated from: When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the Transition Loss = 2(VIN)2IO(MAX)CRSS(f) LTC1772. These items are illustrated graphically in the Other losses including CIN and COUT ESR dissipative layout diagram in Figure 6. Check the following in your losses, and inductor core losses, generally account for layout: less than 2% total additional loss. 1. Is the Schottky diode closely connected between ground (Pin 2) and drain of the external MOSFET?
Foldback Current Limiting
2. Does the (+) plate of C As described in the Output Diode Selection, the worst-case IN connect to the sense resistor as closely as possible? This capacitor provides AC dissipation occurs with a short-circuited output when the current to the MOSFET. diode conducts the current limit value almost continu- ously. To prevent excessive heating in the diode, foldback 3. Is the input decoupling capacitor (0.1µF) connected current limiting can be added to reduce the current in closely between VIN (Pin 5) and ground (Pin 2)? proportion to the severity of the fault. 4. Connect the end of RSENSE as close to VIN (Pin 5) as Foldback current limiting is implemented by adding diodes possible. The VIN pin is the SENSE+ of the current DFB1 and DFB2 between the output and the ITH/RUN pin as comparator. shown in Figure 5. In a hard short (VOUT = 0V), the current 5. Is the trace from SENSE– (Pin 4) to the Sense resistor kept short? Does the trace connect close to RSENSE? VOUT LTC1772 6. Keep the switching node PGATE away from sensitive R2 + I V small signal nodes. TH/RUN FB DFB1 R1 7. Does the V D FB pin connect directly to the feedback FB2 resistors? The resistive divider R1 and R2 must be 1772 F05 connected between the (+) plate of COUT and signal ground.
Figure 5. Foldback Current Limiting
VIN 1 6 + ITH/RUN PGATE CIN LTC1772 R L1 2 5 SENSE RITH GND VIN VOUT M1 0.1µF + 3 4 D1 COUT C V SENSE– ITH FB R1 R2 1772 F06 BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 6. LTC1772 Layout Diagram (See PC Board Layout Checklist)
1772fb 10
U U W U APPLICATIONS INFORMATION
0.4V, the loss increases from 0.5% to 8% as the load will be reduced to approximately 50% of the maximum current increases from 0.5A to 2A. output current. 5. Transition losses apply to the external MOSFET and
PC Board Layout Checklist
increase at higher operating frequencies and input voltages. Transition losses can be estimated from: When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the Transition Loss = 2(VIN)2IO(MAX)CRSS(f) LTC1772. These items are illustrated graphically in the Other losses including CIN and COUT ESR dissipative layout diagram in Figure 6. Check the following in your losses, and inductor core losses, generally account for layout: less than 2% total additional loss. 1. Is the Schottky diode closely connected between ground (Pin 2) and drain of the external MOSFET?
Foldback Current Limiting
2. Does the (+) plate of C As described in the Output Diode Selection, the worst-case IN connect to the sense resistor as closely as possible? This capacitor provides AC dissipation occurs with a short-circuited output when the current to the MOSFET. diode conducts the current limit value almost continu- ously. To prevent excessive heating in the diode, foldback 3. Is the input decoupling capacitor (0.1µF) connected current limiting can be added to reduce the current in closely between VIN (Pin 5) and ground (Pin 2)? proportion to the severity of the fault. 4. Connect the end of RSENSE as close to VIN (Pin 5) as Foldback current limiting is implemented by adding diodes possible. The VIN pin is the SENSE+ of the current DFB1 and DFB2 between the output and the ITH/RUN pin as comparator. shown in Figure 5. In a hard short (VOUT = 0V), the current 5. Is the trace from SENSE– (Pin 4) to the Sense resistor kept short? Does the trace connect close to RSENSE? VOUT LTC1772 6. Keep the switching node PGATE away from sensitive R2 + I V small signal nodes. TH/RUN FB DFB1 R1 7. Does the V D FB pin connect directly to the feedback FB2 resistors? The resistive divider R1 and R2 must be 1772 F05 connected between the (+) plate of COUT and signal ground.
Figure 5. Foldback Current Limiting
VIN 1 6 + ITH/RUN PGATE CIN LTC1772 R L1 2 5 SENSE RITH GND VIN VOUT M1 0.1µF + 3 4 D1 COUT C V SENSE– ITH FB R1 R2 1772 F06 BOLD LINES INDICATE HIGH CURRENT PATHS
Figure 6. LTC1772 Layout Diagram (See PC Board Layout Checklist)
1772fb 10