Datasheet LTC2472 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | Selectable 208sps/833sps, 16-Bit ΔΣ ADCs with 10ppm/°C Max Precision Reference |
| Páginas / Página | 22 / 7 — block DiagraM. Figure 1. Functional Block Diagram. applicaTions … |
| Formato / tamaño de archivo | PDF / 387 Kb |
| Idioma del documento | Inglés |
block DiagraM. Figure 1. Functional Block Diagram. applicaTions inForMaTion. CONVERTER OPERATION. Converter Operation Cycle
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LTC2470/LTC2472
block DiagraM
1 2 12 REFOUT COMP VCC 3 CS INTERNAL 5 ΔΣ A/D REFERENCE SPI SCK 9 IN+ CONVERTER INTERFACE 6 SDO (IN) DECIMATING – 4 SINC FILTER SDI ΔΣ A/D 10 IN– CONVERTER (GND) INTERNAL OSCILLATOR REF– 7, 11, 13 DD PACKAGE GND 8 24702 BD 7, 11 MS PACKAGE ( ) PARENTHESIS INDICATE LTC2470
Figure 1. Functional Block Diagram applicaTions inForMaTion CONVERTER OPERATION
POWER-ON RESET
Converter Operation Cycle
CONVERT The LTC2470/LTC2472 are low power, delta sigma, analog to digital converters with a simple SPI interface and a user SLEEP/NAP selected 208sps/833sps output rate (see Figure 1). The LTC2472 has a fully differential input while the LTC2470 is single-ended. Both are pin and software compatible. Their NO CS = LOW? operation is composed of three distinct states: CONVERT, SLEEP/NAP, and DATA INPUT/OUTPUT. The operation begins with the CONVERT state (see Figure 2). Once the YES conversion is finished, the converter automatically pow- ers down (NAP) or under user control, both the converter DATA INPUT/OUTPUT and reference are powered down (SLEEP). The conversion result is held in a static register while the device is in this state. The cycle concludes with the DATA INPUT/OUTPUT 16TH FALLING NO EDGE OF SCK YES state. Once all 16-bits are read or an abort is initiated the OR 24602 F02 CS = HIGH? device begins a new conversion. The CONVERT state duration is determined by the LTC2470/LTC2472 conversion time (nominally 4ms or
Figure 2. LTC2470/LTC2472 State Transition Diagram
1ms depending on the selected output rate). Once started, this operation can not be aborted except by a low power While in the SLEEP/NAP state, when chip select input is supply condition (VCC < 2.1V) which generates an internal HIGH (CS = HIGH), the LTC2470/LTC2472’s converters are power-on reset signal. powered down. This reduces the supply current by approxi- After the completion of a conversion, the LTC2470/LTC2472 mately 70%. While in the NAP state the reference remains enters the SLEEP/NAP state and remains there until the powered up. The user can power down both the reference chip select is LOW (CS = LOW). Following this condition, and the converter by enabling the sleep mode during the the ADC transitions into the DATA INPUT/OUTPUT state. DATA INPUT/OUTPUT state. Once the next conversion is 24702fb For more information www.linear.com/LTC2470 7 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Analog Inputs Power Requirements Digital Inputs and Digital Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Revision History Typical Application Related Parts
block DiagraM
1 2 12 REFOUT COMP VCC 3 CS INTERNAL 5 ΔΣ A/D REFERENCE SPI SCK 9 IN+ CONVERTER INTERFACE 6 SDO (IN) DECIMATING – 4 SINC FILTER SDI ΔΣ A/D 10 IN– CONVERTER (GND) INTERNAL OSCILLATOR REF– 7, 11, 13 DD PACKAGE GND 8 24702 BD 7, 11 MS PACKAGE ( ) PARENTHESIS INDICATE LTC2470
Figure 1. Functional Block Diagram applicaTions inForMaTion CONVERTER OPERATION
POWER-ON RESET
Converter Operation Cycle
CONVERT The LTC2470/LTC2472 are low power, delta sigma, analog to digital converters with a simple SPI interface and a user SLEEP/NAP selected 208sps/833sps output rate (see Figure 1). The LTC2472 has a fully differential input while the LTC2470 is single-ended. Both are pin and software compatible. Their NO CS = LOW? operation is composed of three distinct states: CONVERT, SLEEP/NAP, and DATA INPUT/OUTPUT. The operation begins with the CONVERT state (see Figure 2). Once the YES conversion is finished, the converter automatically pow- ers down (NAP) or under user control, both the converter DATA INPUT/OUTPUT and reference are powered down (SLEEP). The conversion result is held in a static register while the device is in this state. The cycle concludes with the DATA INPUT/OUTPUT 16TH FALLING NO EDGE OF SCK YES state. Once all 16-bits are read or an abort is initiated the OR 24602 F02 CS = HIGH? device begins a new conversion. The CONVERT state duration is determined by the LTC2470/LTC2472 conversion time (nominally 4ms or
Figure 2. LTC2470/LTC2472 State Transition Diagram
1ms depending on the selected output rate). Once started, this operation can not be aborted except by a low power While in the SLEEP/NAP state, when chip select input is supply condition (VCC < 2.1V) which generates an internal HIGH (CS = HIGH), the LTC2470/LTC2472’s converters are power-on reset signal. powered down. This reduces the supply current by approxi- After the completion of a conversion, the LTC2470/LTC2472 mately 70%. While in the NAP state the reference remains enters the SLEEP/NAP state and remains there until the powered up. The user can power down both the reference chip select is LOW (CS = LOW). Following this condition, and the converter by enabling the sleep mode during the the ADC transitions into the DATA INPUT/OUTPUT state. DATA INPUT/OUTPUT state. Once the next conversion is 24702fb For more information www.linear.com/LTC2470 7 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Analog Inputs Power Requirements Digital Inputs and Digital Outputs Timing Characteristics Typical Performance Characteristics Pin Functions Block Diagram Applications Information Package Description Revision History Typical Application Related Parts