Datasheet LTC2383-16 (Analog Devices) - 10

LTC2383-16
APPLICATIONS INFORMATION OVERVIEW
011...111 The LTC2383-16 is a low noise, low power, high speed 16-bit 011...110 BIPOLAR successive approximation register (SAR) ADC. Operating ZERO from a single 2.5V supply, the LTC2383-16 supports a 000...001 large ±2.5V fully differential input range, making it ideal 000...000 111...111 for high performance applications which require a wide 111...110 dynamic range. The LTC2383-16 achieves ±2LSB INL max, no missing codes at 16-bits and 92dB SNR. 100...001 FSR = +FS – –FS OUTPUT CODE (TWO’S COMPLEMENT) 100...000 1LSB = FSR/65536 Fast 1Msps throughput with no cycle latency makes the LTC2383-16 ideally suited for a wide variety of high speed –FSR/2 –1 0V 1 FSR/2 – 1LSB LSB LSB applications. An internal oscillator sets the conversion time, INPUT VOLTAGE (V) 238316 F02 easing external timing considerations. The LTC2383-16 dissipates only 13mW at 1Msps, while an auto power-down
Figure 2. LTC2383-16 Transfer Function
feature is provided to further reduce power dissipation during inactive periods. shown in Figure 3. The diodes at the input provide ESD protection. In the acquisition phase, each input sees ap-
CONVERTER OPERATION
proximately 45pF (CIN) from the sampling CDAC in series with 40Ω (RON) from the on-resistance of the sampling The LTC2383-16 operates in two phases. During the ac- switch. Any unwanted signal that is common to both quisition phase, the charge redistribution capacitor D/A inputs will be reduced by the common mode rejection of converter (CDAC) is connected to the IN+ and IN– pins the ADC. The inputs draw a current spike while charging to sample the differential analog input voltage. A rising the CIN capacitors during acquisition. During conversion, edge on the CNV pin initiates a conversion. During the the analog inputs draw only a small leakage current. conversion phase, the 16-bit CDAC is sequenced through a successive approximation algorithm, effectively comparing the sampled input with binary-weighted fractions of the REF reference voltage (e.g. V R CIN REF/2, VREF/4 … VREF/65536) using ON the differential comparator. At the end of conversion, the IN+ CDAC output approximates the sampled analog input. The ADC control logic then prepares the 16-bit digital output BIAS REF VOLTAGE code for serial transfer. R C ON IN IN–
TRANSFER FUNCTION
The LTC2383-16 digitizes the full-scale voltage of 2 × REF 238316 F03 into 216 levels, resulting in an LSB size of 76µV with
Figure 3. The Equivalent Circuit for the Differential Analog Input of the LTC2383-16
REF = 2.5V. The ideal transfer function is shown in Figure 2. The output data is in 2’s complement format.
INPUT DRIVE CIRCUITS ANALOG INPUT
A low impedance source can directly drive the high im- pedance inputs of the LTC2383-16 without gain error. A The analog inputs of the LTC2383-16 are fully differential high impedance source should be buffered to minimize in order to maximize the signal swing that can be digitized. settling time during acquisition and to optimize the dis- The analog inputs can be modeled by the equivalent circuit tortion performance of the ADC. Minimizing settling time 238316fa 10 For more information www.linear.com/LTC2383-16