Datasheet LTC2262-12 (Analog Devices)
| Fabricante | Analog Devices |
| Descripción | 12-Bit, 150Msps Ultralow Power 1.8V ADC |
| Páginas / Página | 28 / 1 — FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. LTC2262-12 … |
| Formato / tamaño de archivo | PDF / 546 Kb |
| Idioma del documento | Inglés |
FEATURES. DESCRIPTION. APPLICATIONS. TYPICAL APPLICATION. LTC2262-12 2-Tone FFT,. IN = 68MHz and 69MHz
Línea de modelo para esta hoja de datos
Versión de texto del documento
LTC2262-12 12-Bit, 150Msps Ultralow Power 1.8V ADC
FEATURES DESCRIPTION
n 70.5dB SNR The LTC®2262-12 is a sampling 12-bit A/D converter n 88dB SFDR designed for digitizing high frequency, wide dynamic range n Low Power: 146mW signals. The LTC2262-12 is perfect for demanding commu- n Single 1.8V Supply nications applications with AC performance that includes n CMOS, DDR CMOS or DDR LVDS Outputs 70.5dB SNR and 88dB spurious free dynamic range (SFDR). n Selectable Input Ranges: 1VP-P to 2VP-P Ultralow jitter of 0.17psRMS al ows undersampling of IF n 800MHz Full-Power Bandwidth S/H frequencies with excel ent noise performance. n Optional Data Output Randomizer DC specs include ±0.3LSB INL (typical), ±0.1LSB DNL n Optional Clock Duty Cycle Stabilizer (typical) and no missing codes over temperature. The n Shutdown and Nap Modes transition noise is a low 0.3LSBRMS. n Serial SPI Port for Configuration n Pin Compatible 14-Bit and 12-Bit Versions The digital outputs can be either full rate CMOS, double n 40-Pin (6mm × 6mm) QFN Package data rate CMOS, or double data rate LVDS. A separate output power supply al ows the CMOS output swing to
APPLICATIONS
range from 1.2V to 1.8V. The ENC+ and ENC– inputs may be driven differential y n Communications or single-ended with a sine wave, PECL, LVDS, TTL or n Cellular Base Stations CMOS inputs. An optional clock duty cycle stabilizer al- n Software Defined Radios lows high performance at full speed for a wide range of n Portable Medical Imaging clock duty cycles. n Multi-Channel Data Acquisition L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n Nondestructive Testing Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION LTC2262-12 2-Tone FFT,
1.8V
f
1.2V
IN = 68MHz and 69MHz
VDD TO 1.8V 0 OVDD –10 –20 + D11 –30 12-BIT • ANALOG CMOS INPUT CORRECTION OUTPUT –40 PIPELINED • INPUT OR S/H LOGIC DRIVERS ADC CORE –50 – • LVDS D0 –60 –70 OGND AMPLITUDE (dBFS) –80 CLOCK/DUTY –90 CYCLE –100 CONTROL –110 –120 226212 TA01a GND 0 10 20 30 40 50 60 70 150MHz FREQUENCY (MHz) CLOCK 226212 TA01b 226212fc For more information www.linear.com/LTC2262-12 1 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Typical Performance Characteristics Pin Functions Block Diagram Applications Information Related Parts
FEATURES DESCRIPTION
n 70.5dB SNR The LTC®2262-12 is a sampling 12-bit A/D converter n 88dB SFDR designed for digitizing high frequency, wide dynamic range n Low Power: 146mW signals. The LTC2262-12 is perfect for demanding commu- n Single 1.8V Supply nications applications with AC performance that includes n CMOS, DDR CMOS or DDR LVDS Outputs 70.5dB SNR and 88dB spurious free dynamic range (SFDR). n Selectable Input Ranges: 1VP-P to 2VP-P Ultralow jitter of 0.17psRMS al ows undersampling of IF n 800MHz Full-Power Bandwidth S/H frequencies with excel ent noise performance. n Optional Data Output Randomizer DC specs include ±0.3LSB INL (typical), ±0.1LSB DNL n Optional Clock Duty Cycle Stabilizer (typical) and no missing codes over temperature. The n Shutdown and Nap Modes transition noise is a low 0.3LSBRMS. n Serial SPI Port for Configuration n Pin Compatible 14-Bit and 12-Bit Versions The digital outputs can be either full rate CMOS, double n 40-Pin (6mm × 6mm) QFN Package data rate CMOS, or double data rate LVDS. A separate output power supply al ows the CMOS output swing to
APPLICATIONS
range from 1.2V to 1.8V. The ENC+ and ENC– inputs may be driven differential y n Communications or single-ended with a sine wave, PECL, LVDS, TTL or n Cellular Base Stations CMOS inputs. An optional clock duty cycle stabilizer al- n Software Defined Radios lows high performance at full speed for a wide range of n Portable Medical Imaging clock duty cycles. n Multi-Channel Data Acquisition L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear n Nondestructive Testing Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION LTC2262-12 2-Tone FFT,
1.8V
f
1.2V
IN = 68MHz and 69MHz
VDD TO 1.8V 0 OVDD –10 –20 + D11 –30 12-BIT • ANALOG CMOS INPUT CORRECTION OUTPUT –40 PIPELINED • INPUT OR S/H LOGIC DRIVERS ADC CORE –50 – • LVDS D0 –60 –70 OGND AMPLITUDE (dBFS) –80 CLOCK/DUTY –90 CYCLE –100 CONTROL –110 –120 226212 TA01a GND 0 10 20 30 40 50 60 70 150MHz FREQUENCY (MHz) CLOCK 226212 TA01b 226212fc For more information www.linear.com/LTC2262-12 1 Document Outline Features Description Applications Typical Application Absolute Maximum Ratings Pin Configuration Typical Performance Characteristics Pin Functions Block Diagram Applications Information Related Parts