Datasheet LTC2240-10 (Analog Devices) - 5
| Fabricante | Analog Devices |
| Descripción | 10-Bit, 170Msps ADC |
| Páginas / Página | 28 / 5 — DIGITAL INPUTS AND DIGITAL OUTPUTS The. denotes the specifi cations which … |
| Formato / tamaño de archivo | PDF / 480 Kb |
| Idioma del documento | Inglés |
DIGITAL INPUTS AND DIGITAL OUTPUTS The. denotes the specifi cations which apply over the
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LTC2240-10
DIGITAL INPUTS AND DIGITAL OUTPUTS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LOGIC OUTPUTS (LVDS MODE)
VOD Differential Output Voltage 100Ω Differential Load l 247 350 454 mV VOS Output Common Mode Voltage 100Ω Differential Load l 1.125 1.250 1.375 V
POWER REQUIREMENTS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V DD Analog Supply Voltage (Note 8) l 2.375 2.5 2.625 V PSLEEP Sleep Mode Power SHDN = High, OE = High, No CLK 1 mW PNAP Nap Mode Power SHDN = High, OE = Low, No CLK 28 mW
LVDS OUTPUT MOD
OVDD Output Supply Voltag (Note 8) l 2.375 2.5 2.625 V IVDD Analog Supply Current l 170 185 mA IOVDD Output Supply Current l 58 70 mA PDISS Power Dissipation l 570 638 mW
CMOS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) l 0.5 2.5 2.625 V IVDD Analog Supply Current (Note 7) l 170 185 mA PDISS Power Dissipation 445 mW
TIMING CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 8) l 1 170 MHz tL ENC Low Time (Note 7) Duty Cycle Stabilizer Off l 2.79 2.94 500 ns Duty Cycle Stabilizer On l 1.5 2.94 500 ns tH ENC High Time (Note 7) Duty Cycle Stabilizer Off l 2.79 2.94 500 ns Duty Cycle Stabilizer On l 1.5 2.94 500 ns tAP Sample-and-Hold Aperture Delay 0.4 ns tOE Output Enable Delay (Note 7) l 5 10 ns
LVDS OUTPUT MODE
tD ENC to DATA Delay (Note 7) l 1 1.7 2.8 ns tC ENC to CLKOUT Delay (Note 7) l 1 1.7 2.8 ns DATA to CLKOUT Skew (tC – tD) (Note 7) l –0.6 0 0.6 ns Rise Time 0.5 ns Fall Time 0.5 ns Pipeline Latency 5 Cycles
CMOS OUTPUT MODE
tD ENC to DATA Delay (Note 7) l 1 1.7 2.8 ns tC ENC to CLKOUT Delay (Note 7) l 1 1.7 2.8 ns 224010fb 5
DIGITAL INPUTS AND DIGITAL OUTPUTS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS LOGIC OUTPUTS (LVDS MODE)
VOD Differential Output Voltage 100Ω Differential Load l 247 350 454 mV VOS Output Common Mode Voltage 100Ω Differential Load l 1.125 1.250 1.375 V
POWER REQUIREMENTS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 9) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V DD Analog Supply Voltage (Note 8) l 2.375 2.5 2.625 V PSLEEP Sleep Mode Power SHDN = High, OE = High, No CLK 1 mW PNAP Nap Mode Power SHDN = High, OE = Low, No CLK 28 mW
LVDS OUTPUT MOD
OVDD Output Supply Voltag (Note 8) l 2.375 2.5 2.625 V IVDD Analog Supply Current l 170 185 mA IOVDD Output Supply Current l 58 70 mA PDISS Power Dissipation l 570 638 mW
CMOS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) l 0.5 2.5 2.625 V IVDD Analog Supply Current (Note 7) l 170 185 mA PDISS Power Dissipation 445 mW
TIMING CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 8) l 1 170 MHz tL ENC Low Time (Note 7) Duty Cycle Stabilizer Off l 2.79 2.94 500 ns Duty Cycle Stabilizer On l 1.5 2.94 500 ns tH ENC High Time (Note 7) Duty Cycle Stabilizer Off l 2.79 2.94 500 ns Duty Cycle Stabilizer On l 1.5 2.94 500 ns tAP Sample-and-Hold Aperture Delay 0.4 ns tOE Output Enable Delay (Note 7) l 5 10 ns
LVDS OUTPUT MODE
tD ENC to DATA Delay (Note 7) l 1 1.7 2.8 ns tC ENC to CLKOUT Delay (Note 7) l 1 1.7 2.8 ns DATA to CLKOUT Skew (tC – tD) (Note 7) l –0.6 0 0.6 ns Rise Time 0.5 ns Fall Time 0.5 ns Pipeline Latency 5 Cycles
CMOS OUTPUT MODE
tD ENC to DATA Delay (Note 7) l 1 1.7 2.8 ns tC ENC to CLKOUT Delay (Note 7) l 1 1.7 2.8 ns 224010fb 5