Datasheet LTC1608 (Analog Devices) - 7
| Fabricante | Analog Devices |
| Descripción | High Speed, 16-Bit, 500ksps Sampling A/D Converter with Shutdown |
| Páginas / Página | 20 / 7 — FU CTIO AL BLOCK DIAGRA. TEST CIRCUITS. Load Circuits for Access Timing. … |
| Formato / tamaño de archivo | PDF / 816 Kb |
| Idioma del documento | Inglés |
FU CTIO AL BLOCK DIAGRA. TEST CIRCUITS. Load Circuits for Access Timing. Load Circuits for Output Float Delay
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LTC1608
U U W FU CTIO AL BLOCK DIAGRA
2.2µF 10µF 5V 10µF 5V 10µF 10Ω + + + 3 36 35 9 10 V AV REF DD AVDD DVDD DGND SHDN 33 CS 32 CONTROL µP LOGIC CONVST 31 REFCOMP CONTROL 4 7.5k AND 2.5V RD 30 1.75X LINES TIMING + 4.375V REF BUSY 27 22µF OVDD 29 5V OR + 3V 10µF + OGND 28 1 AIN + DIFFERENTIAL 16-BIT OUTPUT ANALOG INPUT B15 TO B0 – SAMPLING 16-BIT ± BUFFERS 2.5V 2 AIN ADC – D15 TO D0 PARALLEL BUS 11 TO 26 AGND AGND AGND AGND VSS 5 6 1608 BD 7 8 34 10µF + –5V
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 1k 1k DN DN DN DN 1k CL CL 1k CL CL (A) Hi-Z TO VOH AND VOL TO VOH (B) Hi-Z TO VOL AND VOH TO VOL (A) VOH TO Hi-Z (B) VOL TO Hi-Z 1608 TC01 1608 TC02
U U W U APPLICATIO S I FOR ATIO CONVERSION DETAILS
During the conversion, the internal differential 16-bit capacitive DAC output is sequenced by the SAR from the The LTC1608 uses a successive approximation algorithm Most Significant Bit (MSB) to the Least Significant Bit and internal sample-and-hold circuit to convert an analog (LSB). Referring to Figure 1, the A + and A – inputs are signal to a 16-bit parallel output. The ADC is complete with IN IN acquired during the acquire phase and the comparator a sample-and-hold, a precision reference and an internal offset is nulled by the zeroing switches. In this acquire clock. The control logic provides easy interface to micro- phase, a duration of 480ns will provide enough time for the processors and DSPs. (Please refer to the Digital Interface sample-and-hold capacitors to acquire the analog signal. section for the data format.) During the convert phase, the comparator zeroing switches Conversion start is controlled by the CS and CONVST open, putting the comparator into compare mode. The inputs. At the start of the conversion, the successive input switches connect the CSMPL capacitors to ground, approximation register (SAR) resets. Once a conversion transferring the differential analog input charge onto the cycle has begun, it cannot be restarted. summing junctions. This input charge is successively 7
U U W FU CTIO AL BLOCK DIAGRA
2.2µF 10µF 5V 10µF 5V 10µF 10Ω + + + 3 36 35 9 10 V AV REF DD AVDD DVDD DGND SHDN 33 CS 32 CONTROL µP LOGIC CONVST 31 REFCOMP CONTROL 4 7.5k AND 2.5V RD 30 1.75X LINES TIMING + 4.375V REF BUSY 27 22µF OVDD 29 5V OR + 3V 10µF + OGND 28 1 AIN + DIFFERENTIAL 16-BIT OUTPUT ANALOG INPUT B15 TO B0 – SAMPLING 16-BIT ± BUFFERS 2.5V 2 AIN ADC – D15 TO D0 PARALLEL BUS 11 TO 26 AGND AGND AGND AGND VSS 5 6 1608 BD 7 8 34 10µF + –5V
TEST CIRCUITS Load Circuits for Access Timing Load Circuits for Output Float Delay
5V 5V 1k 1k DN DN DN DN 1k CL CL 1k CL CL (A) Hi-Z TO VOH AND VOL TO VOH (B) Hi-Z TO VOL AND VOH TO VOL (A) VOH TO Hi-Z (B) VOL TO Hi-Z 1608 TC01 1608 TC02
U U W U APPLICATIO S I FOR ATIO CONVERSION DETAILS
During the conversion, the internal differential 16-bit capacitive DAC output is sequenced by the SAR from the The LTC1608 uses a successive approximation algorithm Most Significant Bit (MSB) to the Least Significant Bit and internal sample-and-hold circuit to convert an analog (LSB). Referring to Figure 1, the A + and A – inputs are signal to a 16-bit parallel output. The ADC is complete with IN IN acquired during the acquire phase and the comparator a sample-and-hold, a precision reference and an internal offset is nulled by the zeroing switches. In this acquire clock. The control logic provides easy interface to micro- phase, a duration of 480ns will provide enough time for the processors and DSPs. (Please refer to the Digital Interface sample-and-hold capacitors to acquire the analog signal. section for the data format.) During the convert phase, the comparator zeroing switches Conversion start is controlled by the CS and CONVST open, putting the comparator into compare mode. The inputs. At the start of the conversion, the successive input switches connect the CSMPL capacitors to ground, approximation register (SAR) resets. Once a conversion transferring the differential analog input charge onto the cycle has begun, it cannot be restarted. summing junctions. This input charge is successively 7