Datasheet LTC1418 (Analog Devices) - 9

LTC1418
BLOCK DIAGRAM
CSAMPLE A + IN VDD: 5V CSAMPLE VSS: 0V FOR UNIPOLAR MODE A – IN –5V FOR BIPOLAR MODE 8k 2.5V ZEROING SWITCHES VREF 2.5V REF + REF AMP 14-BIT CAPACITIVE DAC COMP – 4.096V REFCOMP 14 SUCCESSIVE APPROXIMATION SHIFT • D13 • REGISTER REGISTER • D0 AGND D3/(SCLK) INTERNAL DGND MUX CONTROL LOGIC CLOCK D1/(DOUT) 1418 BD D4 (EXTCLKIN) D0 (EXT/INT) SHDN CONVST RD CS SER/PAR D2/(CLKOUT) BUSY NOTE: PIN NAMES IN PARENTHESES REFER TO SERIAL MODE
APPLICATIONS INFORMATION CONVERSION DETAILS
C + SAMPLE SAMPLE The LTC1418 uses a successive approximation algorithm A + IN HOLD ZEROING SWITCHES and an internal sample-and-hold circuit to convert an ana- C – SAMPLE HOLD log signal to a 14-bit parallel or serial output. The ADC is SAMPLE A – IN complete with a precision reference and an internal clock. HOLD HOLD The control logic provides easy interface to microproces- C + DAC sors and DSPs (please refer to Digital Interface section + for the data format). C – DAC COMP V + DAC Conversion start is controlled by the CS and CONVST – inputs. At the start of the conversion the successive ap- – proximation register (SAR) is reset. Once a conversion VDAC 14 OUTPUT D13 SAR LATCH cycle has begun it cannot be restarted. D0 1418 F01 During the conversion, the internal differential 14-bit
Figure 1. Simplified Block Diagram
capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). 1418fa For more information www.linear.com/LTC1418 9 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Package/Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs and Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Test Circuit Block Diagram Applications Information Package Description Package Description Revision History Typical Application Related Parts