Datasheet LTC1407, LTC1407A (Analog Devices) - 4

FabricanteAnalog Devices
DescripciónSerial 12-Bit/14-Bit, 3Msps Simultaneous Sampling ADCs with Shutdown
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DIGITAL INPUTS AND DIGITAL OUTPUTS. The. denotes the specifi cations which apply over the

DIGITAL INPUTS AND DIGITAL OUTPUTS The denotes the specifi cations which apply over the

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LTC1407/LTC1407A
DIGITAL INPUTS AND DIGITAL OUTPUTS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDD = 3V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage VDD = 3.3V l 2.4 V VIL Low Level Input Voltage VDD = 2.7V l 0.6 V IIN Digital Input Current VIN = 0V to VDD l ±10 μA CIN Digital Input Capacitance 5 pF VOH High Level Output Voltage VDD = 3V, IOUT = –200μA l 2.5 2.9 V VOL Low Level Output Voltage VDD = 2.7V, IOUT = 160μA 0.05 V VDD = 2.7V, IOUT = 1.6mA l 0.10 0.4 V IOZ Hi-Z Output Leakage DOUT VOUT = 0V to VDD l ±10 μA COZ Hi-Z Output Capacitance DOUT 1 pF ISOURCE Output Short-Circuit Source Current VOUT = 0V, VDD = 3V 20 mA ISINK Output Short-Circuit Sink Current VOUT = VDD = 3V 15 mA
POWER REQUIREMENTS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. With internal reference, VDD = 3V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage 2.7 3.6 V IDD Supply Current Active Mode, fSAMPLE = 1.5Msps l 4.7 7.0 mA Active Mode (LTC1407H/LTC1407AH) l 5.2 8.0 mA Nap Mode l 1.1 1.5 mA Nap Mode (LTC1407H/LTC1407AH) l 1.2 1.8 mA Sleep Mode (LTC1407/LTC1407H) 2.0 15 μA Sleep Mode (LTC1407A/LTC1407AH) 2.0 10 μA PD Active Mode with SCK in Fixed State (Hi or Lo) 12 mW
TIMING CHARACTERISTICS The
l
denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. VDD = 3V. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE(MAX) Maximum Sampling Frequency per Channel l 1.5 MHz (Conversion Rate) tTHROUGHPUT Minimum Sampling Period (Conversion + Acquisiton Period) l 667 ns tSCK Clock Period (Note 16) l 19.6 10000 ns tCONV Conversion Time (Note 6) 32 34 SCLK cycles t1 Minimum Positive or Negative SCLK Pulse Width (Note 6) 2 ns t2 CONV to SCK Setup Time (Notes 6, 10) 3 10000 ns t3 SCK Before CONV (Note 6) 0 ns t4 Minimum Positive or Negative CONV Pulse Width (Note 6) 4 ns t5 SCK to Sample Mode (Note 6) 4 ns t6 CONV to Hold Mode (Notes 6, 11) 1.2 ns 1407fb 4