LTC1287 WUTYPICAL PERFOR A CE CHCARA TERISTICSMaximum Clock Rate vs SourceMinimum Clock Rate for 0.1LSBMaximum Filter Resistor vs CycleResistanceError**Time 500 10k VCC = 3V VCC = 3V R V FILTER REF = 2.5V 0.25 VIN + 400 CLK = 500kHz ) C Ω 1k FILTER ≥1µF – 0.20 *** ( 300 0.15 FILTER 100 200 0.10 +VIN +IN 10 MAXIMUM R 100 RSOURCE– –IN MINIMUM CLK FREQUENCY (MHz) 0.05 MAXIMUM CLK FREQUENCY* (MHz) 0 1 100 1k 10k 100k –50 –25 0 25 50 75 100 10 100 1000 10000 RSOURCE– (Ω) AMBIENT TEMPERATURE (°C) CYCLE TIME (µs) LTC G10 LTC1287 G11 LTC1287 G12 Sample-and-Hold AcquisitionInput Channel Leakage Current vsTime vs Source ResistanceTemperatureNoise Error vs Reference Voltage 100 1000 1.0 V LTC1287 NOISE = 200µV µs) REF = 2.5V 900 GUARANTEED P-P V 0.9 CC = 3V TA = 25°C 800 0.8 0V TO 2.5V INPUT STEP 700 0.7 600 R 0.6 SOURCE+ 10 VIN + 500 0.5 – 400 0.4 300 0.3 200 ON CHANNEL 0.2 PEAK-TO-PEAK NOISE ERROR (LSB) S & H ACQUISITION TIME TO 0.02% ( 100 INPUT CHANNEL LEAKAGE CURRENT (nA) OFF CHANNEL 0.1 1 0 0 100 1k 10k –50 –30 –10 10 30 50 70 90 110 130 0 0.5 1.0 1.5 2.0 2.5 3.0 RSOURCE+ (Ω) AMBIENT TEMPERATURE (°C) REFERENCE VOLTAGE (V) LTC1287 G13 LTC1287 G14 LTC1287 G15 * MAXIMUM CLK FREQUENCY REPRESENTS THE CLK FREQUENCY AT WHICH A 0.1LSB *** MAXIMUM RFILTER REPRESENTS THE FILTER RESISTOR VALUE AT WHICH A 0.1LSB SHIFT IN THE ERROR AT ANY CODE TRANSITION FROM ITS 500kHz VALUE IS FIRST DETECTED. CHANGE IN FULL SCALE ERROR FROM ITS VALUE AT RFILTER = 0Ω IS FIRST DETECTED. ** AS THE CLK FREQUENCY IS DECREASED FROM 1MHz, MINIMUM CLK FREQUENCY (∆ERROR ≤ 0.1LSB) REPRESENTS THE FREQUENCY AT WHICH A 0.1LSB SHIFT IN ANY CODE TRANSITION FROM ITS 500kHz VALUE IS FIRST DETECTED. UUUPI FU CTIO SCS (Pin 1): Chip Select Input. A logic low on this input DOUT (Pin 6): Digital Data Output. The A/D conversion enables the LTC1287. result is shifted out of this output. +IN, –IN (Pin 2,3): Analog Inputs. These inputs must be CLK (Pin 7): Shift Clock. This clock synchronizes the serial free of noise with respect to GND. data transfer. GND (Pin 4): Analog Ground GND should be tied directly VCC (Pin 8): Positive Supply. This supply must be kept free to an analog ground plane. of noise and ripple by bypassing directly to the analog ground plane. VREF (Pin 5): Reference Input. The reference input defines the span of the A/D converter and must be kept free of noise with respect to GND. 1287fa 5