Datasheet LTC1282 (Analog Devices) - 10
| Fabricante | Analog Devices |
| Descripción | 3V 140ksps 12-Bit Sampling A/D Converter with Reference |
| Páginas / Página | 24 / 10 — FU TIO AL BLOCK DIAGRA. APPLICATI. S I FOR ATIO. CONVERSION DETAILS. … |
| Formato / tamaño de archivo | PDF / 370 Kb |
| Idioma del documento | Inglés |
FU TIO AL BLOCK DIAGRA. APPLICATI. S I FOR ATIO. CONVERSION DETAILS. Figure 1. A. IN Input
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LTC1282
U U W FU TIO AL BLOCK DIAGRA
SAMPLE V V DD SS (–3V FOR BIPOLAR MODE, C AGND FOR UNIPOLAR MODE) SAMPLE COMPARATOR SAMPLE A – IN HOLD + D11 12 12 SUCCESSIVE OUTPUT • 12-BIT APPROXIMATION • LATCHES CAPACITIVE REGISTER • VREF(OUT) DAC D0/8 BUSY 1.2V REFERENCE CS INTERNAL CONTROL RD CLOCK LOGIC AGND DGND HBEN LTC1282 • FBD
O U U W U APPLICATI S I FOR ATIO CONVERSION DETAILS
feedback switch opens, putting the comparator into the compare mode. The input switch switches CSAMPLE to The LTC1282 uses a successive approximation and an ground, injecting the analog input charge to the summing internal sample-and-hold circuitry to convert an analog junction. This input charge is successively compared with signal to a 12-bit parallel or 2-byte output. The ADC is the binary-weighted charges supplied by the capacitive complete with a precision reference and an internal clock. DAC. Bit decisions are made by the high speed comparator. The control logic provides easy interface to microproces- At the end of a conversion, the DAC output balances the AIN sors and DSPs. Please refer to the Digital Interface section input charge. The SAR contents (a 12-bit data word) which for the data format. represent the AIN are loaded into the 12-bit latch. Conversion start is controlled by the CS, RD and HBEN inputs. At the start of conversion the successive approxi- SAMPLE mation register (SAR) is reset and the three-state data C SI outputs are enabled. Once a conversion cycle has begun SAMPLE SAMPLE A – it cannot be restarted. IN HOLD During conversion, the internal 12-bit capacitive DAC + output is sequenced by the SAR from the most significant CDAC COMPARATOR DAC bit (MSB) to the least significant bit (LSB). Referring to VDAC S Figure 1, the AIN input connects to the sample-and-hold A capacitor during the sample phase, and the comparator R offset is nulled by the feedback switch. In this sample phase, a minimum delay of 1.14µs will provide enough 12-BIT LATCH LTC1282 • F01 time for the sample-and-hold capacitor to acquire the
Figure 1. A
analog signal. During the convert phase, the comparator
IN Input
10
U U W FU TIO AL BLOCK DIAGRA
SAMPLE V V DD SS (–3V FOR BIPOLAR MODE, C AGND FOR UNIPOLAR MODE) SAMPLE COMPARATOR SAMPLE A – IN HOLD + D11 12 12 SUCCESSIVE OUTPUT • 12-BIT APPROXIMATION • LATCHES CAPACITIVE REGISTER • VREF(OUT) DAC D0/8 BUSY 1.2V REFERENCE CS INTERNAL CONTROL RD CLOCK LOGIC AGND DGND HBEN LTC1282 • FBD
O U U W U APPLICATI S I FOR ATIO CONVERSION DETAILS
feedback switch opens, putting the comparator into the compare mode. The input switch switches CSAMPLE to The LTC1282 uses a successive approximation and an ground, injecting the analog input charge to the summing internal sample-and-hold circuitry to convert an analog junction. This input charge is successively compared with signal to a 12-bit parallel or 2-byte output. The ADC is the binary-weighted charges supplied by the capacitive complete with a precision reference and an internal clock. DAC. Bit decisions are made by the high speed comparator. The control logic provides easy interface to microproces- At the end of a conversion, the DAC output balances the AIN sors and DSPs. Please refer to the Digital Interface section input charge. The SAR contents (a 12-bit data word) which for the data format. represent the AIN are loaded into the 12-bit latch. Conversion start is controlled by the CS, RD and HBEN inputs. At the start of conversion the successive approxi- SAMPLE mation register (SAR) is reset and the three-state data C SI outputs are enabled. Once a conversion cycle has begun SAMPLE SAMPLE A – it cannot be restarted. IN HOLD During conversion, the internal 12-bit capacitive DAC + output is sequenced by the SAR from the most significant CDAC COMPARATOR DAC bit (MSB) to the least significant bit (LSB). Referring to VDAC S Figure 1, the AIN input connects to the sample-and-hold A capacitor during the sample phase, and the comparator R offset is nulled by the feedback switch. In this sample phase, a minimum delay of 1.14µs will provide enough 12-BIT LATCH LTC1282 • F01 time for the sample-and-hold capacitor to acquire the
Figure 1. A
analog signal. During the convert phase, the comparator
IN Input
10