Datasheet LTC1282 (Analog Devices) - 9
| Fabricante | Analog Devices |
| Descripción | 3V 140ksps 12-Bit Sampling A/D Converter with Reference |
| Páginas / Página | 24 / 9 — PI FU CTIO S. AIN (Pin 1):. RD (Pin 20):. VREF (Pin 2):. CS (Pin 21):. … |
| Formato / tamaño de archivo | PDF / 370 Kb |
| Idioma del documento | Inglés |
PI FU CTIO S. AIN (Pin 1):. RD (Pin 20):. VREF (Pin 2):. CS (Pin 21):. AGND (Pin 3):. BUSY (Pin 22):. D11-D4 (Pins 4 to 11):
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LTC1282
U U U PI FU CTIO S AIN (Pin 1):
Analog Input. 0V to 2.5V (Unipolar), ±1.25V
RD (Pin 20):
READ Input. This active low signal starts a (Bipolar). conversion when CS and HBEN are low. RD also enables the output drivers when CS is low.
VREF (Pin 2):
+1.20V Reference Output. Bypass to AGND (10µF tantalum in parallel with 0.1µF ceramic).
CS (Pin 21):
The CHIP SELECT Input must be low for the ADC to recognize RD and HBEN inputs.
AGND (Pin 3):
Analog Ground.
BUSY (Pin 22):
The BUSY Output shows the converter
D11-D4 (Pins 4 to 11):
Three-State Data Outputs. D11 status. It is low when a conversion is in progress. is the Most Significant Bit.
V DGND (Pin 12):
Digital Ground.
SS (Pin 23):
Bipolar Mode — Negative Supply, – 3V. Bypass to AGND with 0.1µF ceramic.
D3/11-D0/8 (Pins 13 to 16):
Three-State Data Outputs. Unipolar Mode — Tie to DGND.
NC (Pins 17 and 18):
No Connection.
VDD (Pin 24):
Positive Supply, 3V. Bypass to AGND (10µF
HBEN (Pin 19):
High Byte Enable Input. This pin is used tantalum in parallel with 0.1µF ceramic). to multiplex the internal 12-bit conversion result into the lower bit outputs (D7 and D0/8). See Table 1. HBEN also disables conversion start when HIGH.
Table 1. Data Bus Output, CS and RD = LOW Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 13 Pin 14 Pin 15 Pin 16
MNEMONIC* D11 D10 D9 D8 D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8 HBEN = LOW DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 HBEN = HIGH DB11 DB10 DB9 DB8 LOW LOW LOW LOW DB11 DB10 DB9 DB8 *D11...D0/8 are the ADC data output pins. DB11...DB0 are the 12-bit conversion results, DB11 is the MSB.
TEST CIRCUITS Load Circuits for Access Time Load Circuits for Output Float Delay
5V 5V 3k 3k DBN DBN DBN DBN 3k CL CL 3k 10pF 10pF DGND DGND DGND DGND (A) Hi-Z TO VOH, (t3) (B) Hi-Z TO VOL, (t3) (A) VOH TO Hi-Z (B) VOL TO Hi-Z AND VOL TO VOH, (t6) AND VOH TO VOL, (t6) 1282 TC02 1282 TC01 9
U U U PI FU CTIO S AIN (Pin 1):
Analog Input. 0V to 2.5V (Unipolar), ±1.25V
RD (Pin 20):
READ Input. This active low signal starts a (Bipolar). conversion when CS and HBEN are low. RD also enables the output drivers when CS is low.
VREF (Pin 2):
+1.20V Reference Output. Bypass to AGND (10µF tantalum in parallel with 0.1µF ceramic).
CS (Pin 21):
The CHIP SELECT Input must be low for the ADC to recognize RD and HBEN inputs.
AGND (Pin 3):
Analog Ground.
BUSY (Pin 22):
The BUSY Output shows the converter
D11-D4 (Pins 4 to 11):
Three-State Data Outputs. D11 status. It is low when a conversion is in progress. is the Most Significant Bit.
V DGND (Pin 12):
Digital Ground.
SS (Pin 23):
Bipolar Mode — Negative Supply, – 3V. Bypass to AGND with 0.1µF ceramic.
D3/11-D0/8 (Pins 13 to 16):
Three-State Data Outputs. Unipolar Mode — Tie to DGND.
NC (Pins 17 and 18):
No Connection.
VDD (Pin 24):
Positive Supply, 3V. Bypass to AGND (10µF
HBEN (Pin 19):
High Byte Enable Input. This pin is used tantalum in parallel with 0.1µF ceramic). to multiplex the internal 12-bit conversion result into the lower bit outputs (D7 and D0/8). See Table 1. HBEN also disables conversion start when HIGH.
Table 1. Data Bus Output, CS and RD = LOW Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 13 Pin 14 Pin 15 Pin 16
MNEMONIC* D11 D10 D9 D8 D7 D6 D5 D4 D3/11 D2/10 D1/9 D0/8 HBEN = LOW DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 HBEN = HIGH DB11 DB10 DB9 DB8 LOW LOW LOW LOW DB11 DB10 DB9 DB8 *D11...D0/8 are the ADC data output pins. DB11...DB0 are the 12-bit conversion results, DB11 is the MSB.
TEST CIRCUITS Load Circuits for Access Time Load Circuits for Output Float Delay
5V 5V 3k 3k DBN DBN DBN DBN 3k CL CL 3k 10pF 10pF DGND DGND DGND DGND (A) Hi-Z TO VOH, (t3) (B) Hi-Z TO VOL, (t3) (A) VOH TO Hi-Z (B) VOL TO Hi-Z AND VOL TO VOH, (t6) AND VOH TO VOL, (t6) 1282 TC02 1282 TC01 9